Digital counter ($c^{+}=(c+1)\mathrm{mod}M$)

A digital counter is a finite-state circuit that increments its stored value on each qualifying clock or event. A binary $w$-bit implementation naturally has modulus $2^w$. Dividing counted ticks by a known clock frequency gives a time interval, subject to wrap ambiguity and sampling accuracy.

Coupled digital counters sharing one clock, with a slower stage enabled by a terminal-state decode of a faster stage. Both stages sample the old state at the same clock edge. An enable changes whether a stage advances; it does not create a separate clock from a combinational decode.

A digital counter following a Gray code, so adjacent output states differ in exactly one bit. The two-bit cycle $00,01,11,10$ is implemented by D flip-flops with next-state functions $G^{+}=H$, $H^{+}=\neg G$.

A hardware timer uses a clock signal to measure intervals, commonly by a digital counter with capture or comparison facilities. A comparison event can request an interrupt or change an output directly. Counter resolution, wraparound, interrupt latency and the hardware's comparison semantics determine the timing guarantees available to software.