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An addressing mode specifies how an instruction obtains an operand or forms an effective memory address. Examples include immediate operands, processor register operands, base-plus-displacement memory access and scaled processor register indexing.

An immediate operand is a value encoded in an instruction rather than fetched from a processor register or a separate memory location. Its width and interpretation limit the available values; scaling an encoded field can trade address granularity for displacement range.

The following original schematic shows the two data organisations. Register-address, write-enable and memory controls are common background; the diagram highlights the changed combinational logic paths.

In the parallel design the result-source multiplexer selects either the arithmetic logic unit or barrel shifter. Its control is additional to the ALU function and shift amount. (i) Addition: read the two operands, select ALU addition and select the ALU result; the shift amount is irrelevant. (ii) Constant left bit shift: read the operand to be shifted, set the shift amount from the immediate operand and select the barrel shifter result; the ALU operation is irrelevant.

In the serial design the result comes through the ALU, so that result-source selection disappears. Its shift-amount control is now relevant to arithmetic as well. (i) Addition: set the barrel shifter to zero shift and select ALU addition, so its inputs are the unshifted processor register values. (ii) Constant left bit shift: set the requested shift and select an ALU operation that passes the shifted operand through. If the ALU lacks that operation, implement it or provide a selectable zero on its other input and add zero. This requirement should be stated, rather than assuming that an ordinary two-input add automatically performs a shift alone.

The ALU result can still supply the memory address. For a register-result instruction, enable processor register writeback and leave memory writes disabled. If the ISA requires shift carry flags, the flag-generation control must retain the barrel shifter's outgoing-bit information; blindly using a pass-through ALU's arithmetic carry is insufficient.

SP-relative addressing forms an effective memory address by adding an offset to the stack pointer. It accesses local variables, saved processor registers or other stack-frame data without dedicating a separate base processor register for each object. The supplied reference gives word-aligned SP-relative offsets from $0$ to $1020$, which corresponds to an eight-bit nonnegative field scaled by four.

In the modified datapath, select the stack pointer for the unshifted ALU input, the instruction immediate operand for the barrel shifter input, and ALU addition. The effective address can then be $\mathrm{SP}+(\mathrm{imm}\ll s)$. Scaling the immediate operand changes the reachable displacement range without storing a larger immediate operand. For example, an eight-bit field shifted by two reaches offsets through $255\times 4=1020$; shifting it by four reaches through $4080$, but only on a sixteen-byte grid. Larger range and finer address granularity are different properties, so the extra reach is not free arbitrary-byte addressing.

The parallel layout cannot feed a shifted immediate operand directly into its address-producing ALU in the same pass. The serial layout can. The actual immediate operand width and permitted shift encodings of a new instruction must be specified; the question does not fix them, so no particular enlarged instruction encoding is implied.

SP-relative addressing adds an encoded displacement to the stack pointer. Scaling an immediate operand by a power of two reaches farther with the same field width but restricts the address grid. An eight-bit nonnegative field scaled by four reaches $0,4,\dots ,1020$, whereas scaling it by sixteen reaches $0,16,\dots ,4080$; it does not provide every intervening byte address.