Use two history D flip-flops. Write , and for the signals just before the active clock edge; update the history by and . Two or more of the three samples are one exactly when some pair are both one, so the majority function is
Three two-input AND gates and one three-input OR gate implement this disjunctive normal form. If a registered output is wanted, feed the expression to the D input of another D flip-flop and capture it at the same edge as the history update. All right-hand sides use the pre-edge values, so no extra sample of delay is introduced.
The three terms are necessary in a minimal sum of products: the input triples , and must each be covered, and a single product covering two of them would also cover a triple having only one one. Thus the minimum is three products, each with two Boolean literals.
Figure 1.
Sample history and registered output for the three digital smoother designs
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