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For an NMOS transistor network described by a series-parallel expression in conducting inputs, replace series by parallel, parallel by series, and each device by a PMOS transistor driven by the same input. De Morgan's laws show recursively that the resulting pull-up network conducts exactly when the original pull-down network does not. This proves complementary rail connections for stable binary inputs in the ideal static model. Factoring a Boolean function before constructing its dual can remove duplicated devices: $ab\vee bc=b(a\vee c)$ needs three lower and three upper devices, instead of four of each. Physical switching transients, device sizing and delays are additional engineering questions.

The two lower conducting branches are the series pairs controlled by $a,b$ and by $c,d$. Their overall NMOS transistor conduction condition is $ab\vee cd$. Apply complementary CMOS network duality: the upper network has the parallel pair of PMOS transistors controlled by $a,b$, in series with the parallel pair controlled by $c,d$. Its first end connects to the high rail, its last end connects to $z$, and the junction between the two pairs is internal to the upper network.

The left panel gives that completion. Every upper transistor uses its correspondingly named input and conducts when that input is low. Its conducting condition is $(\neg a\vee \neg b)\wedge (\neg c\vee \neg d)$, exactly the complement of the lower condition. Thus the ideal static circuit connects the output to one supply rail for every stable binary input.

Joining the two middle nodes makes the upper lower-network transistors, controlled by $a,c$, parallel with each other. The lower transistors, controlled by $b,d$, are also parallel. These two parallel groups are in series, so the lower conducting condition becomes $(a\vee c)\wedge (b\vee d)$.

Its dual upper network must be two parallel branches, one containing the series PMOS transistor pair $a,c$, the other the series pair $b,d$. This is the right panel of the original drawing. Its condition is $(\neg a\wedge \neg c)\vee (\neg b\wedge \neg d)$. Merely leaving the old upper network unchanged would break CMOS complementarity for some inputs, allowing a supply short rather than defining the required logic.

The lower NMOS transistor network conducts through either the $a,b$ series branch or the $b,c$ series branch. Complete the upper PMOS transistor network by the series-parallel dual: between $V_{dd}$ and an intermediate node put $p(a)$ and $p(b)$ in parallel, and between that node and $z$ put $p(b)$ and $p(c)$ in parallel. There are four upper transistors, complementing the four lower transistors. Use the usual body ties to the corresponding supply rails. Each $p(x)$ denotes a PMOS transistor controlled by input $x$, so it conducts when $x=0$.

The upper conducting condition is $(\neg a\vee \neg b)\wedge (\neg b\vee \neg c)$, exactly the complement of $ab\vee bc$. Thus for every stable input the output has a conducting path to exactly one rail in the ideal static CMOS model. The left panel below specifies the added network independently of the source drawing; join its lower terminal to the existing output.

Factor the common input before constructing the networks. Use an NMOS transistor controlled by $b$ in series with parallel NMOS transistors controlled by $a$ and $c$. Its conducting condition remains $b(a\vee c)$. The complementary upper network is a PMOS transistor controlled by $b$ in parallel with a series chain of PMOS transistors controlled by $a$ and $c$; its conducting condition is $\neg b\vee \neg a\neg c$.

This is the right panel in part (a). It uses three lower plus three upper transistors, six in total instead of eight, and needs no separate inverter or complemented external input. The complementary CMOS network duality ensures the same static Boolean function and complementary rail connections.

In the ideal digital switch model, an enhancement-mode PMOS transistor controlled by a low gate signal conducts, and a high gate signal disconnects its channel. The input's conducting literal is therefore negated relative to an NMOS transistor. Complementary PMOS transistors form the high-supply network of static CMOS gates.

A pull-up network connects a logic output to the high supply rail when its conducting condition holds. In static complementary CMOS, it is built from PMOS transistors and paired with a complementary pull-down network.