MOSFET

A metal-oxide-semiconductor field-effect transistor, with an insulating layer separating the gate from the semiconductor. Its gate electric field controls the channel's mobile charge carriers; a semiconductor inversion layer can form a two-dimensional electron gas.

In the ideal digital switch model, an enhancement-mode PMOS transistor controlled by a low gate signal conducts, and a high gate signal disconnects its channel. The input's conducting literal is therefore negated relative to an NMOS transistor. Complementary PMOS transistors form the high-supply network of static CMOS gates.

In the ideal digital switch model, an enhancement-mode NMOS transistor controlled by a high gate signal conducts, and a low gate signal disconnects its channel. Series devices implement logical conjunction of conducting conditions; parallel devices implement logical disjunction. An NMOS transistor pull-down network connects a CMOS output to the low supply rail.

For an n-channel MOSFET, assume a gradual channel, constant charge carrier mobility $\mu$, gate capacitance per area $C_{\mathrm{ox}}$, width $W$ and length $L$. With overdrive $V_{\mathrm{ov}}=V_{GS}-V_T>0$, the inversion-sheet charge magnitude is $C_{\mathrm{ox}}(V_{\mathrm{ov}}-V(x))$. The drift-current relation $I_D=\mu W{C}_{\mathrm{ox}}(V_{\mathrm{ov}}-V)V^{\prime }$ is constant along the channel. Integrating from $V=0$ to $V_{DS}$ over length $L$ proves the displayed expression for $0\le V_{DS}\le V_{\mathrm{ov}}$. At the drain pinch-off condition $V_{DS}=V_{\mathrm{ov}}$, it yields $I_{D,\mathrm{sat}}=\mu C_{\mathrm{ox}}W{V}_{\mathrm{ov}}^2/(2L)$. This ideal saturation neglects channel-length modulation and short-channel velocity saturation.

An ideal insulating gate blocks particle exchange between the gate and substrate of a MOSFET. Their electrochemical potentials, represented by their band-diagram Fermi levels, therefore need not coincide. An applied gate voltage fixes their difference; with $e>0$ and voltage defined by an electron reservoir, ${\tilde{\mu }}_g-{\tilde{\mu }}_s=-e{V}_g$. Contact work-function differences also affect band bending, so equal Fermi levels do not imply flat bands. Each conducting region can separately have a spatially constant equilibrium electrochemical potential.

An integrated circuit technology using complementary MOSFETs. CMOS names a circuit technology; active-pixel sensor names a detector architecture.

A static CMOS implementation of a NAND gate has a pull-down network of NMOS transistors in series and a pull-up network of PMOS transistors in parallel. With $k$ inputs it uses $k$ devices of each kind. All inputs high connect the output to ground; any low input breaks the pull-down path and connects the output to the positive supply through its corresponding p-channel device.

For an NMOS transistor network described by a series-parallel expression in conducting inputs, replace series by parallel, parallel by series, and each device by a PMOS transistor driven by the same input. De Morgan's laws show recursively that the resulting pull-up network conducts exactly when the original pull-down network does not. This proves complementary rail connections for stable binary inputs in the ideal static model. Factoring a Boolean function before constructing its dual can remove duplicated devices: $ab\vee bc=b(a\vee c)$ needs three lower and three upper devices, instead of four of each. Physical switching transients, device sizing and delays are additional engineering questions.

A pull-down network connects a logic output to the low supply rail when its conducting condition holds. In static complementary CMOS, it is built from NMOS transistors; its conducting condition is the negation of the desired output Boolean function.

A pull-up network connects a logic output to the high supply rail when its conducting condition holds. In static complementary CMOS, it is built from PMOS transistors and paired with a complementary pull-down network.

A complementary p-channel/n-channel transistor pair with joined gates as input and joined drains as output. The p-channel device pulls toward the positive supply and the n-channel device toward ground, producing logic inversion with ideally zero settled-state through-current.