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A static CMOS implementation of a NAND gate has a pull-down network of NMOS transistors in series and a pull-up network of PMOS transistors in parallel. With $k$ inputs it uses $k$ devices of each kind. All inputs high connect the output to ground; any low input breaks the pull-down path and connects the output to the positive supply through its corresponding p-channel device.

For an NMOS transistor network described by a series-parallel expression in conducting inputs, replace series by parallel, parallel by series, and each device by a PMOS transistor driven by the same input. De Morgan's laws show recursively that the resulting pull-up network conducts exactly when the original pull-down network does not. This proves complementary rail connections for stable binary inputs in the ideal static model. Factoring a Boolean function before constructing its dual can remove duplicated devices: $ab\vee bc=b(a\vee c)$ needs three lower and three upper devices, instead of four of each. Physical switching transients, device sizing and delays are additional engineering questions.

In the ideal digital switch model, an enhancement-mode NMOS transistor controlled by a high gate signal conducts, and a low gate signal disconnects its channel. Series devices implement logical conjunction of conducting conditions; parallel devices implement logical disjunction. An NMOS transistor pull-down network connects a CMOS output to the low supply rail.

For a CMOS inverter, connect one PMOS transistor from the positive supply $V_{DD}$ to the output and one NMOS transistor from the output to ground; drive both gates with the input $x$. When $x=0$, the PMOS transistor conducts and the NMOS transistor is off; when $x=1$, the reverse holds. Thus the output is $\neg x$, using two transistors.

For a four-input NAND gate, use four NMOS transistors in series between the output and ground, with gates $a,b,c,d$. Use four PMOS transistors in parallel between $V_{DD}$ and the output, with the same gate signals. The pull-down network conducts exactly when all four inputs are one; the pull-up network conducts whenever at least one input is zero. HenceAs usual for static CMOS, tie the NMOS transistor bodies to ground and the PMOS transistor bodies to $V_{DD}$.

A more economical static CMOS design follows from factoring the condition for $z=0$. The output is low exactly when both input pairs disagree:Generate $\neg a,\neg b,\neg c,\neg d$ with four CMOS inverters. Write $n(x)$ or $p(x)$ for an NMOS transistor or PMOS transistor whose gate receives $x$. In the following network expressions, a dash means a series connection and $\parallel$ means a parallel connection.

Connect this eight-device pull-down network between $z$ and ground:The first parallel module conducts exactly when $a\ne c$ and the second exactly when $b\ne d$. Their series connection therefore conducts precisely when $z$ should be zero.

By complementary CMOS network duality, connect this eight-device pull-up network between $V_{DD}$ and $z$:A PMOS transistor conducts when its gate is zero. Consequently the first upper branch conducts when $(\neg a\vee c)\wedge (a\vee \neg c)$, namely $a=c$; the second conducts when $b=d$. Their parallel connection gives the required logical disjunction. For every stable binary input, exactly one of the pull-up network and pull-down network conducts.

The figure labels each MOSFET channel by its gate signal; the four input CMOS inverters are additional to the devices drawn.

A pull-down network connects a logic output to the low supply rail when its conducting condition holds. In static complementary CMOS, it is built from NMOS transistors; its conducting condition is the negation of the desired output Boolean function.

A pull-up network connects a logic output to the high supply rail when its conducting condition holds. In static complementary CMOS, it is built from PMOS transistors and paired with a complementary pull-down network.