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A serial-in parallel-out shift register is a chain of digital registers driven by the same clock signal. At each active clock edge, the first stage captures the input and every later stage captures the preceding stage's old value. Its parallel outputs expose the successive delayed samples simultaneously.

Let $a_n$ be the current sample and, immediately before its sampling edge, let $h_1=a_{n-1},\dots ,h_{k-1}=a_{n-k+1}$. Feed these signals to combinational logic implementing $f$. ThenOnly $k-1$ stored history stages are needed if the current input is used directly. Alternatively, a $k$-stage shift register exposes all $k$ samples after the edge. A separate output digital register can capture the first arrangement at the edge, giving a fully sampled output. Initialize the history, or regard the first $k-1$ cycles as a filling interval.

A shift register accepting one sample at each clock edge and exposing every stored stage as a parallel output.

A chain of digital registers that transfers each stored value to the next stage at a clock edge. A serial-in parallel-out shift register exposes the stored history simultaneously. With the current input and $k-1$ delayed samples, combinational logic can evaluate a function of the latest $k$ samples.