Tachyon by Ciro Santilli 35 Updated +Created
STT_NOTYPE by Ciro Santilli 35 Updated +Created
Then come the most important symbols:
Num:    Value          Size Type    Bind   Vis      Ndx Name
  4: 0000000000000000     0 NOTYPE  LOCAL  DEFAULT    1 hello_world
  5: 000000000000000d     0 NOTYPE  LOCAL  DEFAULT  ABS hello_world_len
  6: 0000000000000000     0 NOTYPE  GLOBAL DEFAULT    2 _start
hello_world string is in the .data section (index 1). It's value is 0: it points to the first byte of that section.
_start is marked with GLOBAL visibility since we wrote:
global _start
in NASM. This is necessary since it must be seen as the entry point. Unlike in C, by default NASM labels are local.
Dynamic section by Ciro Santilli 35 Updated +Created
Contains a lot of different flag masks.
Earth science by Ciro Santilli 35 Updated +Created
E. Coli K-12 MG1655 origin of replication by Ciro Santilli 35 Updated +Created
gothinkster/django-realworld-example-app by Ciro Santilli 35 Updated +Created
As of 2021, last updated 2016, and python 3.5 appears to be mandatory or else:
RuntimeError: __class__ not set defining 'AbstractBaseUser' as <class 'django.contrib.auth.base_user.AbstractBaseUser'>. Was __classcell__ propagated to type.__new__?
which apparently broke in 3.6: stackoverflow.com/questions/41343263/provide-classcell-example-for-python-3-6-metaclass and pyenv install fails on Ubuntu 20.10, so... fuck. Workarounds at:but am I in the mood considering that the ancient Django version would require an immediate port anyways? Repo is at Django 1.0, while newest is now already Django 3. The Rails one is broken for the same reason. Fuck 2.
Parallel light by Ciro Santilli 35 Updated +Created
Often just called collimated light due to the collimator being the main procedure to obtain it.
However, you move very far away from the source, e.g. the Sun, you also get essentially parallel light.
C. elegans cell lineage by Ciro Santilli 35 Updated +Created
Exactly 1033 somatic cells on male, 959 on hermaphrodite, every time, counted as of 2020. A beauty.
Exactly 131 commit apoptosis in the hermaphrodite.
www.wormatlas.org/celllineages.html contains the full lineage as some huge and impossible to view images. This image was taken directly from The embryonic cell lineage of the nematode Caenorhabditis elegans where it is split across many pages, it is a thing of beauty on the PDF.
www.wormatlas.org/celllistsulston.htm contains a non-hierarchical table with the cells and their names.
s-orbital by Ciro Santilli 35 Updated +Created
Electron configuration notation by Ciro Santilli 35 Updated +Created
We will sometimes just write them without superscript, as it saves typing and is useless.
ATP synthase by Ciro Santilli 35 Updated +Created
One of the most beautiful molecular machines known!
The first one with such complexity that was uncovered.
The thing rotates like a water wheel for God's sake, except it uses protons instead of water.
The ATP synthase complex is so large that Power, Sex, Suicide by Nick Lane (2006) page 123 contains a cryoEM image of several ATP synthases on small membrane vesicles, this is the paper: pubs.acs.org/doi/abs/10.1021/bi00437a031# under a fucking paywall.
Video 1.
ATP synthase in action by HarvardX (2017)
Source.
CAM by Ciro Santilli 35 Updated +Created
Using the TLB makes translation faster, because the initial translation takes one access _per TLB level_, which means 2 on a simple 32 bit scheme, but 3 or 4 on 64 bit architectures.
The TLB is usually implemented as an expensive type of RAM called content-addressable memory (CAM). CAM implements an associative map on hardware, that is, a structure that given a key (linear address), retrieves a value.
Mappings could also be implemented on RAM addresses, but CAM mappings may required much less entries than a RAM mapping.
For example, a map in which:
  • both keys and values have 20 bits (the case of a simple paging schemes)
  • at most 4 values need to be stored at each time
could be stored in a TLB with 4 entries:
linear  physical
------  --------
00000   00001
00001   00010
00010   00011
FFFFF   00000
However, to implement this with RAM, _it would be necessary to have 2^20 addresses_:
linear  physical
------  --------
00000   00001
00001   00010
00010   00011
... (from 00011 to FFFFE)
FFFFF   00000
which would be even more expensive than using a TLB.
Process memory layout by Ciro Santilli 35 Updated +Created
For each process, the virtual address space looks like this:
------------------ 2^32 - 1
Stack (grows down)
v v v v v v v v v
------------------

(unmapped)

------------------ Maximum stack size.


(unmapped)


-------------------
mmap
-------------------


(unmapped)


-------------------
^^^^^^^^^^^^^^^^^^^
brk (grows up)
-------------------
BSS
-------------------
Data
-------------------
Text
-------------------

------------------- 0
The kernel maintains a list of pages that belong to each process, and synchronizes that with the paging.
If the program accesses memory that does not belong to it, the kernel handles a page-fault, and decides what to do:
  • if it is above the maximum stack size, allocate those pages to the process
  • otherwise, send a SIGSEGV to the process, which usually kills it
When an ELF file is loaded by the kernel to start a program with the exec system call, the kernel automatically registers text, data, BSS and stack for the program.
The brk and mmap areas can be modified by request of the program through the brk and mmap system calls. But the kernel can also deny the program those areas if there is not enough memory.
brk and mmap can be used to implement malloc, or the so called "heap".
mmap is also used to load dynamically loaded libraries into the program's memory so that it can access and run it.
Calculating exact addresses Things are complicated by:
Single level paging scheme numerical translation example by Ciro Santilli 35 Updated +Created
Suppose that the OS has setup the following page tables for process 1:
entry index   entry address       page address   present
-----------   ------------------  ------------   -------
0             CR3_1 + 0      * 4  0x00001        1
1             CR3_1 + 1      * 4  0x00000        1
2             CR3_1 + 2      * 4  0x00003        1
3             CR3_1 + 3      * 4                 0
...
2^20-1        CR3_1 + 2^20-1 * 4  0x00005        1
and for process 2:
entry index   entry address       page address   present
-----------   -----------------   ------------   -------
0             CR3_2 + 0      * 4  0x0000A        1
1             CR3_2 + 1      * 4  0x12345        1
2             CR3_2 + 2      * 4                 0
3             CR3_2 + 3      * 4  0x00003        1
...
2^20-1        CR3_2 + 2^20-1 * 4  0xFFFFF        1
Before process 1 starts running, the OS sets its cr3 to point to the page table 1 at CR3_1.
When process 1 tries to access a linear address, this is the physical addresses that will be actually accessed:
linear     physical
---------  ---------
00000 001  00001 001
00000 002  00001 002
00000 003  00001 003
00000 FFF  00001 FFF
00001 000  00000 000
00001 001  00000 001
00001 FFF  00000 FFF
00002 000  00003 000
FFFFF 000  00005 000
To switch to process 2, the OS simply sets cr3 to CR3_2, and now the following translations would happen:
linear     physical
---------  ---------
00000 002  0000A 002
00000 003  0000A 003
00000 FFF  0000A FFF
00001 000  12345 000
00001 001  12345 001
00001 FFF  12345 FFF
00004 000  00003 000
FFFFF 000  FFFFF 000
Step-by-step translation for process 1 of logical address 0x00000001 to physical address 0x00001001:
  • split the linear address into two parts:
    | page (20 bits) | offset (12 bits) |
    So in this case we would have:
    *page = 0x00000. This part must be translated to a physical location.
    *offset = 0x001. This part is added directly to the page address, and is not translated: it contains the position _within_ the page.
  • look into Page table 1 because cr3 points to it.
  • The hardware knows that this entry is located at RAM address CR3 + 0x00000 * 4 = CR3:
    *0x00000 because the page part of the logical address is 0x00000
    *4 because that is the fixed size in bytes of every page table entry
  • since it is present, the access is valid
  • by the page table, the location of page number 0x00000 is at 0x00001 * 4K = 0x00001000.
  • to find the final physical address we just need to add the offset:
      00001 000
    + 00000 001
      ---------
      00001 001
    because 00001 is the physical address of the page looked up on the table and 001 is the offset.
    We shift 00001 by 12 bits because the pages are always aligned to 4KiB.
    The offset is always simply added the physical address of the page.
  • the hardware then gets the memory at that physical location and puts it in a register.
Another example: for logical address 0x00001001:
  • the page part is 00001, and the offset part is 001
  • the hardware knows that its page table entry is located at RAM address: CR3 + 1 * 4 (1 because of the page part), and that is where it will look for it
  • it finds the page address 0x00000 there
  • so the final address is 0x00000 * 4k + 0x001 = 0x00000001
The problem with single-level paging by Ciro Santilli 35 Updated +Created
The problem with a single-level paging scheme is that it would take up too much RAM: 4G / 4K = 1M entries _per_ process.
If each entry is 4 bytes long, that would make 4M _per process_, which is too much even for a desktop computer: ps -A | wc -l says that I am running 244 processes right now, so that would take around 1GB of my RAM!
For this reason, x86 developers decided to use a multi-level scheme that reduces RAM usage.
The downside of this system is that is has a slightly higher access time, as we need to access RAM more times for each translation.
Corpuscular theory of light by Ciro Santilli 35 Updated +Created
The Quantum Story by Jim Baggott (2011) page 2 mentions how newton's support for the corpuscular theory of light led it to be held for a very long time, even when evidence of the wave theory of light was becoming overwhelming.
Kavli Institute for Theoretical Physics by Ciro Santilli 35 Updated +Created
Intangible asset by Ciro Santilli 35 Updated +Created
JTAG by Ciro Santilli 35 Updated +Created

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