The Machiavellian Stack Overflow contributor Updated 2025-07-16
- always upvote questions you care about, to increase the probability that they will get answered
- never upvote other people's answers unless you might gain from it somehow, otherwise you are just giving other high reputation users more reputation relative to you
- only mark something to close or as a duplicate if it will bring you some advantage, because closing things creates enemies, especially if the OP has a high profileOne example advantage is if you have already answered the question (and the duplicate as well in case of duplicates), because this will prevent competitors from adding new better answers to overtake you.
- protect questions you've answered whenever someone with less than 10 reputation answers it with a bad answer, to prevent other good contributors from coming along and beating you
- when you find a duplicate pool answer every question with similar answers.Alter each answer slightly to avoid the idiotic duplicate answer detector.If one of the question closes, it is not too bad, as it continues netting you to upvotes, and prevents new answers from coming in.
- follow on Twitter/RSS someone who comments on the top features of new software releases. E.g. for Git, follow GitHub on Twitter, C++ on Reddit. Then run back to any question which has a new answer.
- always upvote the question when you answer it:
- the more upvotes, more likely people are to click it.
- the OP is more likely to see your answer and feel good and upvote you
- if a niche question only has few answers and you come with a good one, upvote the existing ones by other high profile users.This may lead to them upvoting or liking you.
- always upvote comments that favor you:
- "I like this answer!" on your answers
- "also look at that question" when you have answered that question
- if you answer a question by newbie without 15 reputation, find their other questions if any and upvote them, so that the OP can upvote your answer in addition to just accepting
- if a question has 50 million answers and you answer it (often due to a new feature), make a comment on the question pointing to your answer
- if you get a downvote, always leave a comment asking why. It is not because you care about their useless opinion, but because other readers might see the comment, feel sorry for you, and upvote.
- ask any questions under a separate anonymous accounts. Because:
- intelligent people are born knowing, and don't ever ask any questions, so that would hurt your reputation
- downvoting questions does not take 1 reputation away from the downvoter, and so it greatly opens the door for your opponents to downvote you without any cost.
Trie Created 2025-05-29 Updated 2025-07-16
Sample implementations:
Verilator Updated 2025-07-16
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with
assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.Some simulation examples under verilog.
First install Verilator. On Ubuntu:Tested on Verilator 4.038, Ubuntu 22.04.
sudo apt install verilatorRun all examples, which have assertions in them:
cd verilator
make runFile structure is for example:
- verilog/counter.v: Verilog file
- verilog/counter.cpp: C++ loop which clocks the design and runs tests with assertions on the outputs
- verilog/counter.params: gcc compilation flags for this example
- verilog/counter_tb.v: Verilog version of the C++ test. Not used by Verilator. Verilator can't actually run out
_tbfiles, because they do in Verilog IO things that we do better from C++ in Verilator, so Verilator didn't bother implementing them. This is a good thing.
Example list:
- verilog/negator.v, verilog/negator.cpp: the simplest non-identity combinatorial circuit!
- verilog/counter.v, verilog/counter.cpp: sequential hello world. Synchronous active high reset with active high enable signal. Adapted from: www.asic-world.com/verilog/first1.html
- verilog/subleq.v, verilog/subleq.cpp: subleq one instruction set computer with separated instruction and data RAMs