 Solution

A more economical static CMOS design follows from factoring the condition for $z=0$. The output is low exactly when both input pairs disagree:Generate $\neg a,\neg b,\neg c,\neg d$ with four CMOS inverters. Write $n(x)$ or $p(x)$ for an NMOS transistor or PMOS transistor whose gate receives $x$. In the following network expressions, a dash means a series connection and $\parallel$ means a parallel connection.

Connect this eight-device pull-down network between $z$ and ground:The first parallel module conducts exactly when $a\ne c$ and the second exactly when $b\ne d$. Their series connection therefore conducts precisely when $z$ should be zero.

By complementary CMOS network duality, connect this eight-device pull-up network between $V_{DD}$ and $z$:A PMOS transistor conducts when its gate is zero. Consequently the first upper branch conducts when $(\neg a\vee c)\wedge (a\vee \neg c)$, namely $a=c$; the second conducts when $b=d$. Their parallel connection gives the required logical disjunction. For every stable binary input, exactly one of the pull-up network and pull-down network conducts.

The figure labels each MOSFET channel by its gate signal; the four input CMOS inverters are additional to the devices drawn.