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The time from a triggering clock edge to the corresponding settled output of a flip-flop, under specified loading. The time available between successive active clock edges must accommodate this delay, the combinational critical path, the receiving flip-flop's setup time, and any clock uncertainty.

A fixed-width collection of flip-flops storing a binary representation. A synchronous load-enabled digital register captures all its input bits on the active clock edge when load is asserted and otherwise retains its old value. One multiplexer before each D flip-flop can select new data or feedback from its old output. A processor register is a particular use inside a processor; temporary state in a standalone binary multiplier is another.

A flip-flop stores one bit and updates it at a specified clock edge; an asynchronous clear can override that clocked update. Signal polarity is part of the specification, not something inferred from the name alone.

The minimum interval after an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains how quickly a newly launched value may reach the receiving flip-flop.

Use three positive-edge-triggered D flip-flops, all driven by the same clock signal $CLK$. Write the current binary representation as $B2B1B0$, with $B0$ the least significant bit. The next state is the current value plus one when $A=1$ and minus one when $A=0$, in each case modulo eight. A bit toggles under exclusive or with a one.

For upward counting, $B1$ toggles when $B0=1$, while $B2$ toggles when $B1=B0=1$, the respective carry conditions. For downward counting the corresponding borrow conditions are $B0=0$ and $B1=B0=0$. Define the shared inverted direction $N=\neg A$ and the two direction-match signalsEach $T_i$ is one exactly when $Bi=A$: it equals $Bi$ for upward counting and $\neg Bi$ for downward counting. Thus the Boolean functions for the three D inputs areImplement this with two NOT gates for $N,D_0$, four two-input exclusive or gates for $T_0,T_1,D_1,D_2$, and one two-input AND gate. Connect $D_i$ to the D flip-flop whose output is $Bi$; feed the three outputs back into the indicated gates. All three flip-flops capture simultaneously, so each equation uses the old state.

For completeness, the state transition table is

Every three-bit state is valid. A reset may initialize the binary counter to zero if required; counting itself needs no extra state. The direction input must meet the setup time and hold time requirements at the active clock edge.

Use a synchronous binary counter with three positive-edge-triggered D flip-flops, all driven by the same clock signal. Write their outputs $q_2{q}_1{q}_0$, with $q_0$ the least significant bit. The next-state Boolean functions areImplement these with one NOT gate, two exclusive or gates, and one AND gate. Connect each $D_i$ to its corresponding D flip-flop; its output $q_i$ is address line $i$. A reset input clears all three flip-flops to zero, so the first selected sensor is sensor zero.

The state sequence isThe low bit toggles at every clock edge, the middle bit toggles exactly when the old low bit is one, and the high bit toggles exactly when both old lower bits are one. These are precisely the carry conditions for incrementing a three-bit binary representation. Every possible state belongs to the cycle, so there is no unused state requiring recovery. Choose a clock period allowing the combinational logic to settle before the next capture.

A memory read through an address whose contents are fixed during ordinary operation. Used as a Boolean function lookup table, $a$ address bits select one of $2^a$ words, each holding $b$ output bits, so the logical table capacity is $2^{a}b$ bits. A finite-state machine can store its next-state function in such a table while separate flip-flops store the current state.

A cascade in which an output transition of one flip-flop clocks the next. With positive-edge-triggered toggle stages and uncomplemented $Q$ connections, it decrements modulo $2^n$: a zero bit rises to one and propagates a borrow, while a one bit falls to zero and stops propagation. Ripple propagation takes time, so intermediate transient states are not the settled counter state.

The minimum interval before an active clock edge during which the data input of a flip-flop must remain stable for specified operation. It constrains the latest arrival of new data at the receiving flip-flop.