Combinatorial generation 2026-11-05
Combinatorial generation enumerates finite objects satisfying a specified structure, such as permutations, subsets or set partitions. A generation procedure must explain both completeness, meaning every required object appears, and uniqueness, meaning objects are not emitted twice under the chosen equivalence convention. Counting the objects is a different task from writing them all down.
For all length-three binary strings, a Gray code order is 000,001,011,010,110,111,101,100. Consecutive strings differ in exactly one bit. More generally, the reflected binary Gray code is for , using bitwise exclusive or. Its map is invertible: recover each binary digit of by accumulating the exclusive or of the higher Gray code digits. Thus all objects occur exactly once.
A one-bit update can be cheap while reporting a whole object is expensive. Writing every length- binary string explicitly takes at least bit writes, even if the generation state changes only once per object. Useful performance measures therefore distinguish initialization, delay between objects, working memory and the unavoidable output size.
Gray-code counter 2026-10-31
A digital counter following a Gray code, so adjacent output states differ in exactly one bit. The two-bit cycle is implemented by D flip-flops with next-state functions , .
The order is a Gray code through the four vertices of . Applying this identification independently in coordinate pairs makes a spanning subgraph of the hypercube graph . Therefore every vertex boundary in contains the corresponding boundary in .
Joe Sawada Created 2026-10-20 Updated 2026-11-05
Joe Sawada studies combinatorial generation: efficient ways to list all objects in a specified family. His author homepage highlights Gray codes, where consecutive objects differ by a small change, and De Bruijn sequences, which encode many short words through overlapping windows. These viewpoints make the order of generation part of an algorithm's design.[ref]
Karnaugh map 2026-10-25
A truth table arranged so neighbouring cells differ in one Boolean variable, using Gray code order along each multi-bit axis. Opposite edges are also adjacent. A valid group contains all combinations of varying variables while every other variable stays fixed; it eliminates those variables and gives an implicant; covering the one-cells yields a disjunctive normal form. The method is associated with Maurice Karnaugh.
Write for the closed graph neighbourhood of . Since , minimizing the external vertex boundary at fixed cardinality is equivalent to minimizing the closed neighbourhood. The vertex-isoperimetric inequality in a grid says that, among all -vertex subsets of , the first vertices in the simplicial order on a grid minimize this quantity.
We prove the theorem by mathematical induction on , using the allowed two-dimensional case. Fix a coordinate and write for the section in which that coordinate equals . Replace each by the equally large initial simplicial segment . By induction, . The section formula for a grid neighbourhood gives
For the compressed family, are nested initial segments, so the size of their union is the maximum of their sizes. That maximum is no larger than the size of the corresponding uncompressed union. Summing over proves that coordinate compression in a product of paths does not enlarge the boundary.
Apply these compressions in every coordinate, choosing among boundary-minimizing outcomes one with least coordinate-sum weight. If the result were not an initial simplicial segment, it would contain a later vertex while omitting an earlier one. After cancelling coordinates in which they agree, this gives an inversion in a two-coordinate face. Replacing the occupied portion of that face by the equal-size initial segment in does not increase its neighbourhood by the assumed two-dimensional theorem, while it strictly lowers the weight. This contradiction is the local-to-global lemma for simplicial grid order, and completes the induction.
For the second assertion, list the vertices of in the Gray code order
The three consecutive edges form a copy of the four-vertex path . Pairing the binary coordinates and applying this identification in each pair realizes
as a spanning subgraph of the hypercube graph . For any fixed vertex set, adding graph edges can only enlarge its external vertex boundary. Hence a -set in has boundary at least that of the same vertices in , which by hypothesis is at least . Therefore
Arrange each four-variable Karnaugh map in Gray code order down the rows and across the columns. For the row strings are 0100, 0100, ----, 1110; for they are 0001, 1011, ----, 0001. The maps are drawn alongside the state-transition diagram above.
In the map, group the whole ab=01 column to obtain . Group rows 11,10 with columns 00,01 to obtain . Group those same rows with columns 01,11 to obtain . The unused-state row permits these larger groups. Symmetrically, in the map group column ab=10, rows 01,11 with columns 11,10, and those same rows with columns 10,00 (wrapping around the map). This gives
These expressions drive the D inputs of the two D flip-flops. With , both copy their stored bit. With , they force Lt; with , they force Gt. The equations also specify a harmless extension at unused code 11: equal inputs retain it and unequal inputs recover to a valid comparison state. Correct reset is still required. This extension was chosen using don't-cares; the circuit is not claimed to recover from every invalid state without reset.
Let the stored bits be , with most significant. The required Gray code transitions give
Connect directly to the first D flip-flop's data input and feed through one NOT gate to the second input. Drive both enable inputs with and both clock inputs with the same clock. Thus holds both stored bits; takes the next Gray-code counter state at the active clock edge. Reset initializes .
Figure 1.
Enabled Gray-code counter and synchronous SOS sequencer: all stored bits share one clock
. Details.
With ordinary uncomplemented outputs, one NOT gate is minimal: wiring alone cannot produce . If a D flip-flop already provides a complementary output, that output supplies the inversion without an external logic gate. This is a Moore machine because its output depends only on stored state; controls transitions.
Use a synchronous counter cascade, with the three-bit modulo-six counter advancing on every active clock edge and the Gray-code counter advancing only when the old binary state is . Its enable can therefore be
On the six valid binary states, only at . Both digital counters sample the same clock: at an edge leaving , the binary output becomes and simultaneously advances to the next Gray code. At all other edges holds. Starting from , this gives exactly the listed 24-state sequence. Use the shared clock and an enable, rather than making a combinational terminal-state signal into a new clock.[ref]
For the output , every state with has . For , the only extra high states are with binary state , and with binary state or . On valid states these conditions are and , respectively. Hence
The lower circuit in the figure implements this with an AND for , an exclusive or on , an AND with , and an OR with . The resulting Morse code output blocks, in Gray code order , are
Across the two middle blocks these join to three three-clock highs separated by one-clock lows; the first and last blocks provide the three single-clock highs of each S. The specified table is a repeating SOS symbol pattern; its wraparound has a one-clock low, rather than an added inter-message pause. The output is a Moore machine decoding of current stored bits; its value changes after those bits settle.
Use Karnaugh maps with rows and columns , both in Gray code order . Juxtaposition means Boolean conjunction, means Boolean disjunction, and a bar means Boolean negation. The minimal sum of products forms are
and
For , the groups are , and . For , take , , , and the isolated minterm . Every group contains only required ones. The last group wraps between the top and bottom map rows.
These covers are minimal: needs its three essential groups, forced by inputs 6, 3 and 8. For , input 5 is isolated, while 9, 3 and 6 each force their respective pair; input 0 still needs a further group. These five groups also attain the minimum literal count of 16.
Figure 1.
Karnaugh maps for the three decoder outputs used in the solution
. Original maps in Gray order. Invalid inputs are fixed to zero for and ; only the map in part (d) treats them as X. Blue cells are required ones. Details.
Use four-variable Karnaugh maps with rows and columns , both in Gray code order. A dash denotes an unused present state. The maps for the three next-state bits are
For , join its sole one with the dash directly below it. For , use the four-cell groups and , and the two-cell group ; the last group wraps between the top and bottom rows. For , join the one at row , column to the dash below it; the one at row , column is isolated. These prime implicants give
Here products mean Boolean conjunction and sums mean Boolean disjunction. The inputs are the desired next-state bits of the three D flip-flops. The equations are independent of the unused values except for the explicitly chosen Karnaugh map groups.
The steady-state output is . Its Karnaugh map, with rows and columns in Gray code order, is
The existing prime implicants cover adjacent ones except for some transitions in . The consensus theorem supplies the two missing bridging implicants and , giving
Both are needed in a hazard-free sum of products retaining the original terms. At , the two values of require a common implicant, necessarily covered by ; at , the corresponding transition requires . Neither bridge covers the other's critical edge. All other adjacent-one pairs already share a term. Thus two is the least number of additional prime implicants. This addresses single-input static hazards; simultaneous input changes require separate analysis.
The minority Boolean function is one at input assignments . Put on the rows and in Gray code order on the columns. The Karnaugh map has rows and . Pair the cell with each of its three one-cell neighbours; the horizontal pair across the two map edges is valid because those columns are adjacent.
Figure 1.
Three essential pairs in the three-input minority Karnaugh map
. Details.
The pairs give
Generate with three NOT gates. Then use
De Morgan laws show that the final NAND gate computes the required disjunction of the three products. This uses three two-input NAND gates and one three-input NAND gate, besides the input inverters. If only two-input NAND gates are available, replace the final three-input gate by , , .
The three pairs are essential: the one-input assignments each have only as an adjacent one-cell, so no pair can be omitted from this disjunctive normal form.
Write the inputs as and . Each row compares the represented value of with all four values of . In Gray code order along both axes, the Karnaugh map is
The equality cases lie on the diagonal and are all one. A complete row of ones at and a complete column at provide useful checks. The outlined groups are used in the next part.
Figure 1.
Two-bit comparator Karnaugh map with all five essential four-cell groups
. Details.
Steinhaus-Johnson-Trotter algorithm Created 2026-10-20 Updated 2026-11-05
The Steinhaus-Johnson-Trotter algorithm lists all permutations so consecutive entries differ by one adjacent transposition. Start at increasing order with an arrow pointing left on each label. A label is mobile if its arrow points to an adjacent smaller label. Swap the largest mobile label in its arrow direction, then reverse the arrows of every larger label; stop when none is mobile. For three labels this gives 123, 132, 312, 321, 231, 213. Recursively, the largest label sweeps across each smaller-label arrangement in alternating directions, visiting every insertion position once. This gives a Gray code on permutations, useful when an objective can be updated cheaply after a local exchange.