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Current-polarity dead-time compensation adjusts a switching command to oppose the dead-time output-voltage error predicted from the direction of load electric current. During bridge switching dead time, an inductive current can flow through a MOSFET body diode; the resulting rail clamp makes the cycle-average error depend on current direction. The manufacturer’s bridge-state diagrams establish that current-path mechanism.^[ref]

Consider an original ideal half-bridge model with rail separation $V_d$, switching period $T$, duty fraction $D$, and effective dead-time fraction $\delta =t_d/T$. Assume current has one nonzero sign throughout the affected interval and that device drops are negligible. Let positive current leave the midpoint, so that the adopted clamping model givesFor a desired normalized average $D_{\ast }$, chooseSubstitution cancels the average error in this model. The correction changes the commanded pulse duration; it does not remove the nonoverlap needed to avoid H-bridge shoot-through. Different full-bridge switching patterns require applying the appropriate event model to each leg before subtracting the terminal averages.

For $V_d=48\mathrm{V}$, $T=50\mu \mathrm{s}$ and $t_d=0.5\mu \mathrm{s}$, $\delta =0.01$ and the uncompensated error magnitude is $0.48\mathrm{V}$. At $D_{\ast }=0.40$, use $D_{\mathrm{cmd}}=0.41$ for positive current and $0.39$ for negative current. Each gives the intended $19.2\mathrm{V}$ average under the stated assumptions.

Command limits matter. Suppose the allowed duty range ends at $0.98$ because a minimum off-time is required. With positive current and $D_{\ast }=0.975$, the formula asks for $0.985$. Clipping to $0.98$ leaves an actual normalized average of $0.97$, an error of $-0.24\mathrm{V}$ at this bus potential difference. Thus a compensation law can be correct locally while the requested average lies outside its achievable range. Minimum pulse durations impose further limits.

Current-sign uncertainty in dead-time compensation is particularly important near a zero crossing. If an estimated sign $\hat{\sigma }$ is used while the actual sign is $\sigma$, the residual error, before command clipping, isA wrong opposite sign doubles the uncompensated error magnitude: $0.96\mathrm{V}$ in the example. Current-sensor delay, noise and a sign reversal within the switching interval can all invalidate a sign held constant for the cycle. Using a zero correction in an uncertain interval avoids that particular wrong-sign doubling, but does not cancel the original error.

A proposed bench comparison records gate commands, midpoint electric potential difference and load electric current together, then integrates each switching cycle with and without compensation. Compare positive-current, negative-current and crossing intervals separately, and repeat near pulse limits. This separates the average-error cancellation being tested from preservation of nonoverlap, device voltage drops and imperfect knowledge of switching delay.

Dead-time output-voltage error is the difference between the intended switching-cycle average electric potential difference and the actual average produced when nonoverlap intervals alter the terminal waveform. Bridge switching dead time reduces H-bridge shoot-through, but during it an inductive load still carries electric current. Its recirculation path helps determine which rail clamps the output. The primary manufacturer discussion shows the bipolar/unipolar switching states and diode paths during that interval.^[ref]

An original event-accounting model avoids assuming a universal sign. Let an ideal half-bridge output take values 0 and $V_d$ over period $T$. During disjoint affected intervals of lengths $\Delta t_k$, suppose the intended normalized level is $q_k$ and the actual clamped level is $c_k$, each either 0 or 1. ThenAn interval replaced by the same rail contributes no error. An intended high interval replaced by low contributes negatively; the reverse contributes positively. Device drops require additional voltage terms.

For a stipulated single-pulse switching model, assume the load current keeps one sign throughout a cycle and that ideal recirculation clamps the midpoint to the low rail for current leaving the midpoint, or to the high rail for current entering it. With one effective high interval shortened or extended by $t_d$,For $V_d=24\mathrm{V}$, $T=50\mu \mathrm{s}$ and $t_d=100\mathrm{ns}$, the magnitude is $48\mathrm{mV}$. The corresponding ideal duty error magnitude is $t_d/T=0.002$. In a full H-bridge, subtract the two measured midpoint averages; their errors can reinforce or partly cancel according to their states.

Current-polarity dead-time compensation would add an opposing correction in that specified model. Near a current zero crossing, however, the sign may change within the interval, and the assumed clamping model can fail. Blindly applying the same signed offset throughout a crossing need not correct the actual waveform.

A proposed low-voltage test records both switch commands, actual midpoint potential and load electric current, integrates the difference from the intended waveform over a cycle, and compares it with the event sum. Repeat across current directions and pulse widths. Separate switching delay, diode drops and uncertain timing rather than fitting every discrepancy to one nominal dead-time number. The formulas above are illustrative switching models, not specifications for a particular driver.

Bridge switching dead time is an intentional nonoverlap interval between complementary conduction commands in a power-switching leg. It allows the outgoing device to cease conducting before the incoming device conducts, reducing H-bridge shoot-through. The applicable interval depends on propagation and device switching delays, not only on the timestamps of ideal logic commands. Nexperia's primary bridge discussion introduces the delay between turning off one pair and turning on the other, while retaining a path for inductive current.^[ref]

For an original timing bound, command the outgoing device off at $t=0$ and the incoming device on at $t=t_d$. Let ${\tau }_{\mathrm{off},\max }$ be the latest possible end of outgoing conduction, and ${\tau }_{\mathrm{on},\min }$ the earliest incoming conduction delay after its own command. A sufficient nonoverlap condition in this delay model isWith an additional positive timing margin $m$, chooseThe two switching directions can require different bounds. The inputs must cover the operating conditions for which the guarantee is claimed.

Suppose the latest turn-off completion is $80\mathrm{ns}$ and the earliest turn-on delay is $20\mathrm{ns}$. Zero modeled overlap requires at least $60\mathrm{ns}$ of commanded separation; a stipulated $20\mathrm{ns}$ extra margin gives $t_d=80\mathrm{ns}$. Incoming conduction then starts no earlier than $100\mathrm{ns}$, leaving at least $20\mathrm{ns}$ after the outgoing device has ceased. These numbers illustrate the bound rather than a particular gate-driver specification.

Longer separation also changes the output waveform. In an original half-bridge example with rails 0 and $V_d$, suppose one nominal high interval per period is shortened by exactly $t_d$, with the removed interval clamped to the low rail. The mean electric potential difference changes byFor $V_d=24\mathrm{V}$, $T=50\mu \mathrm{s}$ and $t_d=100\mathrm{ns}$, this is $-48\mathrm{mV}$. The dead-time output-voltage error in a complete bridge depends on which intervals are replaced and on load-current direction; this one-pulse calculation does not supply a universal coefficient.

During nonoverlap, the electric current of an inductor cannot disappear instantly. Its path can pass through diodes or other permitted conducting devices, and the midpoint potential depends on that path. A proposed test records both actual transition timing and the resulting terminal waveform under the intended load conditions. It tests the timing margin and output distortion separately, instead of treating an increased programmed delay as a complete characterization.

An H-bridge is a four-switch arrangement that can apply either polarity of a DC supply across a two-terminal electrical load. Two switches form each side, with the load joining their midpoint nodes. Power inverters and bidirectional electric motor drives use this switching geometry. The primary TI lesson illustrates its components, forward/reverse states and inductive-current paths.^[ref]

In an idealized switching model, let $q_A,q_B\in \{0,1\}$ select the lower or upper rail at midpoint A and B, with supply magnitude $V_d$. ThenOpposite choices give $+V_d$ or $-V_d$ across the load. Equal choices give zero terminal difference even though both midpoints can be at the upper rail. This zero-output state does not mean every switch is open.

Each leg's upper and lower devices must not simultaneously provide a low-resistance path between supply rails: that is H-bridge shoot-through. Bridge switching dead time introduces a nonoverlap interval during a transition. Inductive load electric current still needs a path during that interval, often involving diodes or controlled conducting devices. The actual current path depends on the bridge state and current direction.

An original inductor example shows why reversing the commanded terminal polarity need not instantly reverse electric current. Neglect winding electrical resistance and opposing motor electromotive force, and take $L=10\mathrm{mH}$ with initial current $i=2\mathrm{A}$. Applying $v_{AB}=-12\mathrm{V}$ givesCurrent reaches zero only after about $1.667\mathrm{ms}$ if this voltage is maintained. Initially $v_{AB}i=-24\mathrm{W}$: the inductive load is returning stored energy through the bridge rather than absorbing it. Its initial magnetic energy is $L{i}^2/2=0.020\mathrm{J}$.

During rapid ideal bipolar switching, applying $+V_d$ for fraction $d$ and $-V_d$ for the rest gives interval-average output $(2d-1)V_d$. With $V_d=12\mathrm{V}$ and $d=0.75$, the average is $6\mathrm{V}$. This average does not specify instantaneous current or heating without a load model.

A proposed low-voltage observation records both midpoint potentials, differential load electric potential difference and load electric current. Comparing them through reversal distinguishes a changed switch command from changed current direction. Driver delays, device drops, recirculation and the supply's ability to accept returned energy determine how closely a real bridge follows the ideal states.

H-bridge shoot-through is unintended conduction directly between the supply rails through devices in the same bridge leg. It differs from the intended load-current path through opposite legs of an H-bridge. Overlapping device conduction during switching can create that rail-to-rail path even when the intended logical states never command it. The manufacturer application note explicitly identifies cross-conduction as shorting the supply and introduces nonoverlap timing to prevent it.^[ref]

An original lumped fault-loop model shows why a short overlap can matter. Let a previously unenergized parasitic loop have electrical resistance $R$, inductance $L$ and constant supply electric potential difference $V_d$. During overlap,soFor $t\ll \tau$, the initial ramp is $i\simeq V_{d}t/L$; the steady resistive value $V_d/R$ is not reached instantaneously.

Take stipulated $V_d=24\mathrm{V}$, $R=0.10\Omega$ and $L=100\mathrm{nH}$, giving $\tau =1\mu \mathrm{s}$. An overlap lasting $100\mathrm{ns}$ reaches about $22.84\mathrm{A}$. The supply deliversSome of this energy remains in the loop's magnetic field at turn-off; it should not all be labeled heat dissipated in one switch. A $500\mathrm{ns}$ overlap in the same ideal model reaches about $94.43\mathrm{A}$, illustrating the nonlinear dependence on duration. Device and supply behavior can invalidate these constant-parameter assumptions.

Bridge switching dead time addresses timing overlap by allowing one conduction path to cease before the complementary one starts. An inductive load still needs a recirculation path while the controlled devices are off. TI's primary bridge lesson illustrates current paths during that interval.^[ref]

A proposed diagnostic compares actual device control waveforms and supply-current transients with load current during transitions, using a limited-energy test arrangement. A large load current by itself does not identify shoot-through; the timing and path establish the mechanism. The calculated fault-loop pulse is an original model, not an asserted device rating.