Write the bit vector as , with the least significant bit. Its unsigned interpretation of a bit string is , where each . The range is the integers from through ; a leading one contributes positive weight , not a sign.
Each stage has and therefore toggles. The printed clock symbols have no inversion bubble, so they are positive-edge triggered; each later clock is driven by the previous uncomplemented output. Consequently the circuit is a ripple counter that counts down modulo eight. A zero least significant bit rises to one and propagates the transition; a one falls to zero and stops it. For example, the settled transition from is , whereas is followed by .
After input pulses the settled value is , giving
The answers are , , and , respectively, in most-significant-first order. Treating these as falling-edge stages would reverse the counting direction and would not follow the drawn clock symbols.