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A voltage gain determines a power gain only when the electrical conditions at both ports are included. The familiar equality between $20{\log }_{10}|A_v|$ and $10{\log }_{10}{G}_P$ requires a particular impedance relation; it is not a conversion between arbitrary voltage and power ratios.

Use phasors whose moduli are root mean square amplitudes, at one sinusoidal frequency. At a load with electrical impedance $Z$ and electrical admittance $Y=1/Z$, the current is $I=YV$. Its complex electrical power is $V{I}^{\ast }$, with the complex conjugate arising from the relative phase of the two sinusoids. Averaging $v(t)i(t)$ over a cycle gives the active powerTo see the averaging step, write $v(t)=\sqrt{2}|V|\cos (\omega t+{\varphi }_V)$ and similarly for $i(t)$. The product's cycle average is $|V||I|\cos ({\varphi }_V-{\varphi }_I)$, the real part of $V{I}^{\ast }$. Peak-amplitude phasors instead require an extra factor $1/2$.

Let $Y_{\mathrm{in}}$ describe the actual input impedance and $Y_L$ the actual load impedance. Take $\mathrm{Re}{Y}_{\mathrm{in}}>0$ and $\mathrm{Re}{Y}_L>0$ with nonzero terminal signals, and define currents into the amplifier at the input and into the load at the output. With the measured loaded voltage gain $A_v=V_L/V_{\mathrm{in}}$,Thus $G_P=|A_v{|}^2$ requires equality of the relevant electrical conductances, not merely equality of impedance moduli. For example, input $Z_{\mathrm{in}}=50\Omega$ and load $Z_L=(30+40i)\Omega$ both have modulus $50\Omega$, but their electrical admittances have real parts $0.020$ and $0.012\mathrm{S}$. The multiplier is $0.6$, so $G_P=0.6|A_v{|}^2$.

For real resistive ports this becomesTake an original example with measured $|A_v|=0.5$, $R_{\mathrm{in}}=10\mathrm{k\Omega }$ and $R_L=50\Omega$. The voltage gain is $-6.02\mathrm{dB}$, while the power gain is $50$, or $16.99\mathrm{dB}$. An active buffer can reduce the signal's electric potential difference while delivering more signal power than it accepts at its input; the supply provides the additional energy.

The amplifier's output impedance is distinct from the connected load impedance. To show why that distinction matters, model its output by a Thévenin equivalent with open-circuit voltage $A_0{V}_{\mathrm{in}}$ and series resistance $R_o$. The voltage divider givesWith $A_0=0.6$ and $R_o=10\Omega$, the $50\Omega$ load produces the preceding $A_v=0.5$ example. Differentiating $R_L/(R_o+R_L{)}^2$ gives $(R_o-R_L)/(R_o+R_L{)}^3$, so delivered power is largest at $R_L=R_o$, as in the maximum power transfer theorem. Here its power gain is $90$. Increasing $R_L$ much further makes $A_v$ approach $A_0$ but reduces delivered power. That high-load-impedance regime is impedance bridging, useful for sensing the source's voltage with little loading.

A bench demonstration uses a function generator, a known termination and an oscilloscope. The Keysight guide explains that an expected-load setting changes how amplitude is displayed for generators with a fixed series output impedance; a high-impedance load can receive twice the voltage expected for a matched $50\Omega$ termination.^[ref] As an independent low-frequency resistive calculation, an open-circuit source of $1\mathrm{V}$ root mean square with $50\Omega$ series resistance delivers $0.5\mathrm{V}$ and $5\mathrm{mW}$ to $50\Omega$. Into $1\mathrm{M\Omega }$ it delivers about $0.99995\mathrm{V}$ but only $1.00\mu \mathrm{W}$. The larger terminal reading accompanies much less delivered power. Specify the actual load, frequency and amplitude convention when comparing gain measurements.

A reactive-load phase shift in a finite-output-impedance amplifier occurs because the load and output impedance form a frequency-dependent divider. In the model of loaded voltage gain, assume a positive real output resistance $R_o$, an ideal capacitive load $C_L$ and open-circuit gain $A_0$ approximately constant over the band of interest. With $\omega =2\pi f$,The divider follows from the terminal equivalent described by the university circuit notes.^[ref]

Putting $\tau =R_o{C}_L$ givesThus even an ideal capacitor can change both amplitude and phase when the source driving it has finite resistance. Its reactive current and energy exchange are described by complex electrical power; zero average dissipation in the ideal capacitor does not mean zero output-current demand.

For an original example, choose $R_o=100\Omega$, $C_L=10\mathrm{nF}$ and $A_0=10$. Then $\tau =1\mu \mathrm{s}$ and the load pole is $f_p=1/(2\pi \tau )\approx 159.2\mathrm{kHz}$. At that frequency the gain magnitude is $10/\sqrt{2}\approx 7.071$ and the extra phase lag is $45^{\circ }$. A measured input of $10\mathrm{mV}$ root mean square gives about $70.7\mathrm{mV}$ root mean square at the capacitor, requiring approximately $0.707\mathrm{mA}$ root-mean-square capacitive current.

A bench test holds the actual amplifier input fixed while sweeping frequency and compares loaded and unloaded output amplitudes and phases. Include probe capacitance in $C_L$. The group delay introduced by a capacitive amplifier load also matters when comparing pulse waveforms.

This single-pole calculation assumes the stated constant open-circuit gain and resistive output impedance. The complete amplifier may have additional frequency dependence and feedback effects. The manufacturer's ideal feedback-gain examples are defined within their operating assumptions.^[ref] Check the actual output-current and linear operating range before interpreting a departure from this model as a capacitor-only effect.