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Brian Jeff wrote Arm's 2013 overview of its Cortex-A mobile processor roadmap. The article distinguishes architectural generations and implementation choices, explaining the Cortex-A8 as a dual-issue processor that preserves instruction issue order.^[ref]

The distinction is concrete: issuing two independent instructions in a cycle is compatible with maintaining program order. It does not by itself imply out-of-order execution, which permits ready instructions to proceed around stalled ones subject to correctness constraints. This example separates issue width from scheduling policy, two different dimensions of microarchitecture. The attribution here concerns Jeff's identified technical explanation; a product overview is not evidence that its author individually designed every processor it describes.

Clock frequency is the number of cycles of a clock signal per unit time. If its period is $T_c$, its frequency is $f=1/T_c$. A $3\times 10^9$ hertz clock has a nominal period of about $0.333\times 10^{-9}$ seconds. The clock coordinates timed operations; it does not specify how many complete program instructions are performed in each cycle.

For a fixed-frequency processor, execution time can be written as instruction count times average cycles per instruction divided by frequency. Raising frequency can improve that component of runtime, but it may also require a different pipeline organization or increase power and thermal constraints. Memory waits and dependencies can leave some cycles without completed instructions, while superscalar execution can complete several instructions in one cycle. Performance comparisons must therefore include the workload and microarchitecture, not only the clock rating.

Computer architecture studies the organization and behaviour of computers, connecting the operations visible to software with the hardware that executes them. An instruction set architecture specifies the machine-level contract, including instructions, accessible processor registers and addressing behaviour. A microarchitecture is a particular implementation of that contract, including execution units, instruction pipelining and memory caches.^[ref]

Two CPUs can implement the same instruction set architecture while taking different times to run the same computer program. One might overlap independent instructions or use a larger memory cache; neither choice changes what an addition instruction is required to compute. A useful performance model writes execution time as instruction count times average cycles per instruction divided by clock frequency. The factors interact: a design that raises clock frequency can also change cycles per instruction. This separates a program's required behaviour from the engineering choices that determine its cost.

Cycles per instruction is the average number of processor clock cycles spent per counted instruction for a specified execution interval and counting convention. If $N$ instructions complete in $C$ cycles, $\mathrm{CPI}=C/N$. At constant clock frequency $f$, execution time satisfiesFor example, $10^9$ completed instructions at CPI 1.5 and $3\times 10^9$ hertz take 0.5 seconds.

The value depends on instruction mix, dependencies, cache misses, branch behavior and the chosen microarchitecture. It can be less than one when several instructions complete per cycle. A long-latency instruction need not prevent other independent work from overlapping, so individual instruction latencies cannot simply be added to predict elapsed time. Comparing processors by frequency alone ignores both CPI and the number of instructions needed for the same task.

A microarchitecture is a particular hardware organization implementing an instruction set architecture. It specifies mechanisms such as instruction decoding, execution units, pipelines, caches and branch prediction. Two processors can expose the same instruction-set contract while making different choices about those mechanisms.

For example, both processors may correctly execute a load followed by an integer addition. One can overlap independent instructions and obtain the load from a nearby cache, while the other waits for a longer memory access. The architectural result agrees, but cycle counts differ. Speculative work must be discarded or committed in a way that preserves the required visible behavior. This distinction explains why compatibility with one instruction set does not imply equal performance, power consumption or physical implementation.^[ref]