Past exam of the year 1 of the computer science course of the University of Oxford / 2021 / Digital systems, linear algebra, introduction to formal proof / 1 / a

After asserting and releasing the active-low Start pulse, a valid sequence is $X_0\uparrow$, then $X_1\uparrow$, then $X_2\uparrow$, with each input held high through the relevant sampling interval. The first JK flip-flop has $J=X_0,K=0$ and is clocked by $X_1$, so the rising clock edge of $X_1$ samples $X_0=1$ and sets $Y_0=1$. Once that output has settled, a rising clock edge of $X_2$ clocks the second JK flip-flop with $J=Y_0=1,K=0$, setting $Y_1=1$.

The essential conditions concern sampled levels: $X_0$ must be high at a rising clock edge of $X_1$, and $Y_0$ must then be high at a rising clock edge of $X_2$. Separate edges with adequate setup and hold time avoid an ambiguous simultaneous transition.