Past exam of the year 1 of the computer science course of the University of Oxford / 2022 / Digital systems, linear algebra, introduction to formal proof resit / 3 / a

The lower NMOS transistor network conducts through either the $a,b$ series branch or the $b,c$ series branch. Complete the upper PMOS transistor network by the series-parallel dual: between $V_{dd}$ and an intermediate node put $p(a)$ and $p(b)$ in parallel, and between that node and $z$ put $p(b)$ and $p(c)$ in parallel. There are four upper transistors, complementing the four lower transistors. Use the usual body ties to the corresponding supply rails. Each $p(x)$ denotes a PMOS transistor controlled by input $x$, so it conducts when $x=0$.

The upper conducting condition is $(\neg a\vee \neg b)\wedge (\neg b\vee \neg c)$, exactly the complement of $ab\vee bc$. Thus for every stable input the output has a conducting path to exactly one rail in the ideal static CMOS model. The left panel below specifies the added network independently of the source drawing; join its lower terminal to the existing output.