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, the loop can then remain at zero indefinitely. This is a two's complement wraparound example, not a universal language rule for signed overflow. A signed 64-bit doubling variable can represent the first power of two above every positive signed 32-bit input, repairing this particular range. The proof of the mathematical loop and the representation limits are separate parts of its correctness argument.

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Past exam of the mathematics course of the University of Cambridge / 2006 / ia / Paper 5 / 3 / Solution Created 2026-09-24 Updated 2026-10-14

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Extract one four-bit digit at a time, beginning at the most significant end of the Java int. A lookup string supplies characters, but no library performs the conversion:

java
static String toHex(int value) {
    String digits = "0123456789abcdef";
    String answer = "";
    boolean started = false;
    for (int shift = 28; shift >= 0; shift -= 4) {
        int digit = (value >>> shift) & 15;
        if (started || digit != 0 || shift == 0) {
            answer = answer + digits.charAt(digit);
            started = true;
        }
    }
    return answer;
}

The logical right bit shift >>> inserts zeros, and the bit mask 15 retains exactly the low four bits of the shifted word. Each emitted character is therefore the corresponding hexadecimal digit. The started flag suppresses leading zero digits; the shift == 0 exception makes zero produce "0", rather than an empty string.

A negative Java integer uses two's complement. Its top bit is set, so the first extracted digit is between eight and fifteen and all eight digits are emitted. We interpret its original 32-bit pattern, without taking an absolute value or negating a potentially unnegatable minimum integer. In particular, toHex(19) returns "13", toHex(-1) returns "ffffffff", and toHex(Integer.MIN_VALUE) returns "80000000". There are exactly eight iterations, so for this fixed word size the time complexity is constant.

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Past exam of the mathematics course of the University of Cambridge / 2006 / ia / Paper 5 / 8 / b / ii / Solution Created 2026-09-24 Updated 2026-10-14

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Use strength reduction on the disassembled hot instructions. In a fixed-width wrapping integer model,

8 x = x ≪ 3, 15 x = (x ≪ 4) - x (mod 2^{w}) .

(1)

The first replacement is a single left bit shift. For the second, preserve the original operand in a register, shift a copy left by four and subtract the original:

text
rOriginal = x
rResult = rOriginal << 4
rResult = rResult - rOriginal

This avoids a general multiplication if shifts and subtraction are cheaper on the target processor. The two identities hold for positive and negative two's complement operands when only the low

w

result bits are required.

Because only a binary is available, patch the machine instructions and adjust displaced branches or use a jump to a replacement code block if the new sequence does not fit. Preserve live registers and the calling convention. If later instructions consume overflow or other condition flags, or the original multiplication produces a double-width result or traps on overflow, matching only the low-word arithmetic is insufficient: those effects must be reproduced or the transformation rejected. Finally, measure the modified program; a fast hardware multiply need not be slower than several replacement instructions.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2003 / Functional programming, data structures and algorithms, procedural programming, and digital hardware / 10 / a / i / Solution 2026-10-31

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n

-bit two's complement word

b_{n - 1} \dots b_{1} b_{0}

represents the integer

x = - b_{n - 1} 2^{n - 1} + i = 0 \sum n - 2 b_{i} 2^{i}, - 2^{n - 1} \leq x \leq 2^{n - 1} - 1.

(1)

The leading bit has negative weight. Words beginning with zero encode the nonnegative values; words beginning with one encode the negative values. Equivalently, interpret the whole word as unsigned and subtract

2^{n}

when its leading bit is one. For example, the four-bit words 0111, 1000, and 1111 encode

7

- 8

, and

- 1

respectively. The range is asymmetric: the most negative value has no positive counterpart in the same number of bits.

For a nonzero representable magnitude, complementing all bits and adding one obtains its negative modulo

2^{n}

. Fixed-width addition can therefore use the same low-order binary numeral system addition circuitry for signed and unsigned operands; interpreting the result as signed requires detecting integer overflow.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2014 / Digital systems, linear algebra, introduction to formal proof / 1 / a / Solution 2026-10-31

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A MIPS R-type instruction has the 32-bit instruction encoding

6 op 5 rs 5 rt 5 rd 5 shamt 6 funct .

(1)

For add $x,$y,$z, the processor register indices are

rs = y

rt = z

and

rd = x

, while

shamt = 0

. The main opcode selects the R-type family and the function field selects addition. The register file reads its two operands from instruction bits 25:21 and 20:16. In the original datapath, RegDst=1 selects bits 15:11 as the destination, ALUSrc=0 selects the second register file output, and ALUFunc=ADD makes the arithmetic logic unit add its inputs. The result returns to wdata; RegWrite=1 writes it to

x

at the active clock edge. The zero output is irrelevant here.^[ref]

A MIPS I-type instruction instead has the instruction encoding

6 op 5 rs 5 rt 16 immediate .

(2)

For addi $x,$y,n,

rs = y

rt = x

, and the low sixteen bits contain the immediate operand. The register file supplies

y

to the first arithmetic logic unit input. Set RegDst=0 to select bits 20:16 for the destination, and ALUSrc=1 to select the extended immediate operand for the second input. The opcode directly requests addition, so ALUFunc=ADD and RegWrite=1. The second register file read is unused. The returned result is written into

x

The sign extension circuit retains the low sixteen bits and copies bit 15 into all sixteen new high positions:

sext (n)_{15 : 0} = n, sext (n)_{31 : 16} = 16 copies n_{15} \dots n_{15} .

(3)

Thus sign extension preserves the signed two's complement value: 0x7fff becomes 0x00007fff, whereas 0x8000 becomes 0xffff8000. For both instructions, the architectural result above assumes no signed overflow; the full MIPS architecture specifies an overflow exception, which is outside this simplified datapath.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2015 / Digital systems, linear algebra, introduction to formal proof / 5 / d / Solution 2026-10-31

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For the unsigned interpretation of the binary string, the set positions have weights

2^{15}, 2^{13}, 2^{12}, 2^{11}, 2^{10}, 2^{8}, 2^{6}, 2^{5}, 2^{4}

. Thus

u = 2^{15} + 2^{13} + 2^{12} + 2^{11} + 2^{10} + 2^{8} + 2^{6} + 2^{5} + 2^{4} = 48496.

(1)

In 16-bit two's complement, the most significant bit is set, so subtract

2^{16}

from that unsigned interpretation:

z = 48496 - 65536 = - 17040.

(2)

For a half-precision floating-point number, split the fields at their actual boundaries rather than the printed groups of four:

101111 0101110000.

(3)

The sign is negative, the true exponent is

15 - 15 = 0

, and the fraction is

2^{- 2} + 2^{- 4} + 2^{- 5} + 2^{- 6} = 23/64

. It is a normal finite value, so

x = - (1 + 2^{- 2} + 2^{- 4} + 2^{- 5} + 2^{- 6}) 2^{0} = - \frac{87}{64} = - 1.359375.

(4)

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Past exam of the year 1 of the computer science course of the University of Oxford / 2018 / Digital systems, linear algebra, introduction to formal proof / 3 / d / Solution 2026-10-31

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Use the stipulated MIPS I-type instruction encoding, whose unused

r t

field is zero, so register-file output

r d_{1}

supplies the hardwired zero register. With

ALUSrc = 0

and subtraction selected, the arithmetic logic unit computes

R [rs] - 0

. Its zero flag detects

R [rs] = 0

, while bit 31 of

r d_{0}

is the sign in two's complement. Therefore the required signed test is

R [rs] > 0 ⟺ \neg Zero \land \neg r d_{0} [31] .

(1)

Introduce one new control bit

GT

, and replace the zero-flag input to the existing branch XOR by

Z^{*} = Zero \lor (GT \land r d_{0} [31]) .

(2)

This needs an AND gate, an OR gate and a tap of the sign bit. With

GT = 0

, existing branch behavior is unchanged. With

GT = 1

and

Branch = 11

, the existing branch-taken circuit gives

\neg Z^{*}

, exactly the positive test. Its output still selects between

p c + 4

and the usual sign-extended branch target. The complete control row is

bgtz RegDst - Branch 11 Jump 0 MemWrite 0 MemToReg - ALUOp 01 MemRead 0 ALUSrc 0 RegWrite 0 GT 1 .

(3)

Set

GT = 0

for each instruction in parts (a)–(c). Registers and data memory remain unchanged. The available signed slt operation could support a different design; the sign-and-zero design above avoids adding an ALU-input swap and explicitly distinguishes zero from positive values.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2022 / Digital systems, linear algebra, introduction to formal proof / 2 / a / Solution 2026-10-25

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Use the AAPCS32 convention: r0 holds the input address, r1 the length, and r0 receives the result. The following Thumb instruction set assembly language uses only scratch processor registers, so no callee-saved registers need saving. Assume the array is valid, halfword-aligned, and has nonnegative length; for the mathematical sum assume it fits a signed 32-bit two's complement integer.

.syntax unified
.thumb
.thumb_func
sum16:
    movs r2, #0             @ accumulated sum
    cmp  r1, #0
    ble  .Ldone             @ empty array; also returns 0 if n < 0
.Lloop:
    movs r3, #0             @ Thumb signed load needs a register offset
    ldrsh r3, [r0, r3]      @ signed halfword at a; offset read before r3 changes
    adds r2, r2, r3         @ include this signed value
    adds r0, r0, #2         @ advance by one short, not one byte
    subs r1, r1, #1         @ one fewer element remains
    bne  .Lloop
.Ldone:
    movs r0, r2             @ result register
    bx   lr                 @ leaf routine: lr was not overwritten

After

j

iterations, the loop invariant is that r2 contains the first

j

elements' sum, r0 points to element

j

, and r1 is

n - j

. The sign extension in ldrsh supplies the correct signed addend. One iteration preserves this loop invariant, and the decreasing remaining length proves algorithm termination. For the seven-element calls, the sum lies between

- 229376

and

229369

, so it fits. For longer arrays that overflow, these instructions compute the sum modulo

2^{32}

; that is not a claim about defined signed C programming language overflow behavior. The operand forms are those of the paper's reference sheet.^[ref]

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Past exam of the year 1 of the computer science course of the University of Oxford / 2022 / Digital systems, linear algebra, introduction to formal proof / 2 / b / Solution 2026-10-25

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Let the stored bits be

b_{15}, \dots, b_{0}

and let

s = b_{15}

. The sign extension performed by ldrsh keeps output bit

i

equal to

b_{i}

for

0 \leq i \leq 15

, and sets every output bit

16 \leq i \leq 31

s

. Thus a nonnegative halfword gets sixteen leading zero bits, while a negative halfword gets sixteen leading one bits.

Its signed 32-bit two's complement value is

- s 2^{31} + s \sum_{i = 16}^{30} 2^{i} + \sum_{i = 0}^{15} b_{i} 2^{i} = - s 2^{16} + s 2^{15} + \sum_{i = 0}^{14} b_{i} 2^{i} = - s 2^{15} + i = 0 \sum 14 b_{i} 2^{i} .

(1)

The last expression is exactly the original signed 16-bit value. The equality uses the finite geometric series

\sum_{i = 16}^{30} 2^{i} = 2^{31} - 2^{16}

. In particular, simply inserting zero bits would be wrong for a negative halfword: its unsigned interpretation differs from its signed value by

2^{16}

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Past exam of the year 1 of the computer science course of the University of Oxford / 2023 / Digital systems, linear algebra and introduction to formal proof / 1 / a / Solution 2026-10-25

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Write an

n

-bit binary string as

A = a_{n - 1} \dots a_{1} a_{0}

, where each

a_{i} \in {0, 1}

and

a_{n - 1}

is most significant. Its unsigned interpretation and two's complement interpretation are

bin (A) = i = 0 \sum n - 1 a_{i} 2^{i}, twoc (A) = - a_{n - 1} 2^{n - 1} + i = 0 \sum n - 2 a_{i} 2^{i} .

(1)

Equivalently,

twoc (A) = bin (A) - a_{n - 1} 2^{n}

. The ranges are

0

through

2^{n} - 1

and

- 2^{n - 1}

through

2^{n - 1} - 1

, respectively. The same stored bits can therefore denote different integers depending on the chosen interpretation.

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Past exam of the year 1 of the computer science course of the University of Oxford / 2023 / Digital systems, linear algebra and introduction to formal proof / 1 / d / Solution 2026-10-25

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Let

s = 1_{{a < 0}}

, let

b = 1023 s

, and let

u = (a + b) mod 1024

denote the least nonnegative residue. Here

a

is a signed 32-bit two's complement value. The source instructions, annotated with their derived values, are:

rem1024:
    asrs r3, r0, #31    // r3 = -s: all zero bits or all one bits
    lsrs r3, r3, #22    // r3 = b = 1023*s
    adds r0, r0, r3     // r0 = a+b
    lsls r0, r0, #22    // r0 has word value (a+b)*2^22 modulo 2^32
    lsrs r0, r0, #22    // r0 = u = (a+b) modulo 1024, in 0,...,1023
    subs r0, r0, r3     // r0 = u-b
    bx lr              // return u-b

The first instruction is an arithmetic right shift, so it replicates the sign bit. The second is a logical right shift, turning the all-one word into

1023

. The paired shifts then extract the low ten bits, as in (c). Their effect is the residue of

a + b

even if its two's complement interpretation is negative, because

1024

divides the word modulus

2^{32}

. The adjusted value

a + b

is representable for every input: positive inputs are unchanged, and negative inputs gain only

1023

For

a \geq 0

b = 0

, so the return value is the usual nonnegative remainder

a mod 1024

. For

a < 0

, put

t = - a > 0

as a mathematical integer, and write

t = 1024 q + r

with

0 \leq r < 1024

. If

r = 0

, then

u = 1023

and the return value is zero. If

1 \leq r \leq 1023

, then

u = (- t + 1023) mod 1024 = 1023 - r, u - b = - r .

(1)

These are precisely the remainders for C integer division, whose quotient truncates towards zero. In every case the result has the dividend's sign or is zero, has magnitude below

1024

, and satisfies

a = 1024 q_{C} + r_{C}

. The proof includes the smallest representable input:

t = - a

was used only in mathematical reasoning, not as an overflowing machine operation.^[ref]

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Past exam of the year 1 of the computer science course of the University of Oxford / 2023 / Digital systems, linear algebra and introduction to formal proof / 1 / e / Solution 2026-10-25

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Use the same bias, then an arithmetic right shift by ten:

div1024:
    asrs r3, r0, #31    // -1 when a<0, otherwise 0
    lsrs r3, r3, #22    // b = 1023 when a<0, otherwise 0
    adds r0, r0, r3     // a+b, representable for every signed input
    asrs r0, r0, #10    // floor((a+b)/1024)
    bx lr

An arithmetic right shift of a two's complement integer computes division rounded down. For

a \geq 0

, this already equals truncation towards zero. For

a < 0

, the signed power-of-two division by biasing identity is

trunc (a /1024) = ⌊ \frac{a + 1023}{1024} ⌋ .

(1)

Indeed, writing

- a = 1024 q + r

with

0 \leq r < 1024

makes the adjusted numerator

- 1024 q + (1023 - r)

; its quotient rounded down is

- q

for every

r

, including zero. Thus the code returns the signed quotient in all cases and contains no data-dependent branch. The final bx lr simply returns to the caller.

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Radix sort key encoding 2026-10-18

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An encoding for radix sort must make the intended total order of sort keys agree with the lexicographic order of its fixed-width numerical digit tuples. The positional notation for bounded nonnegative integers has this property. At the most significant differing position

m

, a one-unit numerical digit difference contributes

R^{m}

, while all lower positions together contribute at most

(R - 1) \sum_{j = 0}^{m - 1} R^{j} = R^{m} - 1.

(1)

This geometric series shows why lower numerical digits cannot reverse that comparison. Leading zero padding works here because it preserves place values and the represented integer.

For signed integers in a known integer interval

L \leq x \leq U

, encode

e (x) = x - L

and choose

d

with

U - L < R^{d}

. This order-preserving function is also injective:

x < y

exactly when

e (x) < e (y)

. For

- 8 \leq x \leq 7

, the four-bit encodings of

- 8, - 3, - 1, 0, 4, 7

are

0000, 0101, 0111, 1000, 1100, 1111

after adding eight. Restore the original signed sort keys when displaying the complete sorting records; the encoding need not replace their data. Sorting the unsigned values of raw two's complement bit patterns would put nonnegative integers before negative ones, so their representation alone is not this ordered encoding.

For variable-length strings, first specify the alphabet order and whether a proper prefix precedes its extensions. As an original construction, use

a < b

, let every string have length at most three, encode

a

as one and

b

as two, and append zeros to width three. Zero is reserved for an end marker strictly below every real symbol. The strings

ε, a, aa, ab, b

encode as

000, 100, 110, 120, 200

in radix three, which preserves their lexicographic order. A differing real symbol decides the comparison; at a prefix boundary, the shorter string's zero comes before the extension's one or two. Left padding would instead encode

b

002

and

aa

011

, reversing

aa < b

. Padding raw bytes with zero also fails if zero is an allowed data symbol: distinct strings can then receive the same encoding. A reserved end marker and an explicit symbol ordering are essential; byte order alone does not establish a desired human text order.

Figure 1.
Stable ties preserve lower digits; suitable encodings preserve the intended order
. Original counterexample above: reversing a tens tie destroys the units order and a later stable hundreds pass cannot repair it. Below: signed integer offsets and a reserved end marker for bounded strings produce increasing fixed-width encodings. All entries are exact constructed examples. **Details**.

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Signed power-of-two division by biasing 2026-10-25

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For signed two's complement integers, a conditional positive bias converts the rounding behaviour of an arithmetic right shift into C integer division. It can be formed without a conditional branch by turning the sign bit into either zero or a low-

k

-bit bit mask.

Proof. Nonnegative

a

needs no adjustment. If

a < 0

, write

- a = 2^{k} q + r

0 \leq r < 2^{k}

. Then

a + (2^{k} - 1) = - 2^{k} q + (2^{k} - 1 - r)

, whose quotient rounded down is

- q

, exactly the quotient truncated towards zero. The bias fits safely for

1 \leq k < n

in an

n

-bit signed word: it is added only to negative inputs, and the largest possible adjusted input is

2^{k} - 2

. The corresponding remainder is

((a + b) mod 2^{k}) - b

, where

b = (2^{k} - 1) 1_{a < 0}

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Sign extension 2026-10-24

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To widen an

m

-bit two's complement integer to

w > m

bits, preserve the original low bits and fill the new high positions with the old sign bit

s

. The change in signed positional weights is

- s 2^{w - 1} + s \sum_{i = m - 1}^{w - 2} 2^{i} = - s 2^{m - 1}

, so the represented signed value is unchanged. Zero extension instead preserves the unsigned interpretation, and changes the signed value of negative inputs.

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Unsigned interpretation of a bit string 2026-10-25

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For an

n

-bit binary string

A = a_{n - 1} \dots a_{0}

, the unsigned interpretation assigns positive positional weights

2^{i}

to its bits. Its values range from zero to

2^{n} - 1

. The same stored bits have two's complement value

bin (A) - a_{n - 1} 2^{n}

, so interpreting a machine word is a separate choice from storing its bits.

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