Verilator Updated +Created
Verilog simulator that transpiles to C++.
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.
Some simulation examples under verilog.
First install Verilator. On Ubuntu:
sudo apt install verilator
Tested on Verilator 4.038, Ubuntu 22.04.
Run all examples, which have assertions in them:
cd verilator
make run
File structure is for example:
Example list:
Casimir element Updated +Created
Galaxy Updated +Created
Vice Media Updated +Created
Inflection Updated +Created
Optical material property Updated +Created
Human vs computer go Updated +Created
Intelligence Gathering Updated +Created
Power series Updated +Created
Research group Updated +Created
Sexually Updated +Created
Sexual selection Updated +Created
University IP ownership Updated +Created
Ciro Santilli's general feeling is that university should not own IP, it should belong to the researchers. Instead, university should help researchers make their startups, so they can become big, and then we can tax them and reinvest in the universities.
Of course, this goes through the nonprofit impact measurement difficulty. Maybe we could instead limit the IP to some reasonably small percentage, like 10%?
But still, as of 2020, if feels like universities are way too greedy.
French politician Updated +Created
Gang bang Updated +Created
Hydrogen Updated +Created
Slacktivism Updated +Created
Test data 11 Updated +Created
G Updated +Created
Niobium-Titanium Updated +Created

Unlisted articles are being shown, click here to show only listed articles.