 Solution

A D flip-flop stores one bit. At its specified active clock edge, it samples $D$ and, after its clock-to-Q delay, makes $Q$ equal to that sampled value. Between active clock edges it retains the stored value. The input must meet the setup and hold time requirements around the sampling edge; a level-sensitive latch would have different behavior.

For a finite-state sequential circuit, encode the present state in a bank of D flip-flops. Feed their outputs $q$ and the external inputs $u$ to combinational logic computing the next-state function $F(q,u)$, and connect those outputs to the flip-flop $D$ inputs. A common clock signal then performs the simultaneous updateOutput combinational logic computes $H(q)$ for a Moore machine or $H(q,u)$ for a Mealy machine. Since any finite next-state and output table is a Boolean function, it has a Boolean circuit implementation. Initialization specifies the starting state, and unused state encodings require either a recovery rule or an initialization assumption. The clock period must accommodate propagation through the D flip-flops and intervening combinational logic before the next sampling edge.