by

Ciro Santilli (@cirosantilli, 34)

Place and route

Given a bunch of interlinked standard cell library elements from the logic synthesis step, actually decide where exactly they are going to go on 2D (stacked 2D) integrated circuit surface.

Sample output format of place and route would be GDSII.

Table of contents
- Integrated circuit layout Place and route
  - GDSII Integrated circuit layout

Integrated circuit layout

GDSII

Figure 1.
3D rendering of a GDSII file.
Source.

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