OurBigBook
.com (beta)
About
$ Donate
Sign in
Sign up
by
Ciro Santilli
(@cirosantilli,
32
)
Place and route
Given a bunch of interlinked
standard cell library
elements from the
logic synthesis
step, actually decide where exactly they are going to go on 2D (stacked 2D)
integrated circuit
surface.
Sample output format of place and route would be
GDSII
.
Table of contents
Integrated circuit layout
GDSII
Integrated circuit layout
Integrated circuit layout
Place and route
GDSII
Integrated circuit layout
Figure 1
. 3D rendering of a GDSII file.
Source
.
Ancestors
Electronic design automation phase
Electronic design automation
Semiconductor device fabrication
Computer hardware
Computer
Information technology
Area of technology
Technology
Index
Incoming links
Electronic design automation
Standard cell library
Discussion (0)
Subscribe (1)
Sign up
or
sign in
create discussions.
There are no discussions about this article yet.
View article source