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by
Ciro Santilli
(@cirosantilli,
32
)
Logic synthesis
Step of
electronic design automation
that maps the
register transfer level
input (e.g.
Verilog
) to a
standard cell library
.
The output of this step is another
Verilog
file, but one that exclusively uses interlinked cell library components.
Ancestors
Electronic design automation phase
Electronic design automation
Semiconductor device fabrication
Computer hardware
Computer
Information technology
Area of technology
Technology
Index
Incoming links
Electronic design automation
Place and route
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