This is the lowest level of abstraction computer, at which the basic gates and power are described.
At this level, you are basically thinking about the 3D layered structure of a chip, and how to make machines that will allow you to create better, usually smaller, gates.
Video 1. imec: The Semiconductor Watering Hole by Asianometry (2022) Source. A key thing they do is have a small prototype fab that brings in-development equipment from different vendors together to make sure the are working well together. Cool.
What a legendary place.
As mentioned at from Video "Applied Materials by Asianometry (2021)", originally the companies fabs would make their own equipment. But eventually things got so complicated that it became worth it for separate companies to focus on equipment, which then then sell to the fabs.
As of 2020 leading makers of the most important fab photolithography equipment.
Video 1. ASML: TSMC's Critical Supplier by Asianometry (2021) Source.
Video 2. How ASML Won Lithography by Asianometry (2021) Source.
First there were dominant Elmer and Geophysics Corporation of America dominating the market.
Then a Japanese government project managed to make Nikon and Canon Inc. catch up, and in 1989, when Ciro Santilli was born, they had 70% of the market. In 1995, ASML had reached 25% market share. Then it managed the folloging faster than the others:
Parent/predecessor of ASML.
Video 1. Applied Materials by Asianometry (2021) Source. They are chemical vapor deposition fanatics basically.
This is the mantra of the semiconductor industry:
  • power and area are the main limiting factors of chips, i.e., your budget:
    • chip area is ultra expensive because there are sporadic errors in the fabrication process, and each error in any part of the chip can potentially break the entire chip. Although there are
      The percentage of working chips is called the yield.
      In some cases however, e.g. if the error only affects single CPU of a multi-core CPU, then they actually deactivate the broken CPU after testing, and sell the worse CPU cheaper with a clear branding of that: this is called binning,5892.html
    • power is a major semiconductor limit as of 2010's and onwards. If everything turns on at once, the chip would burn. Designs have to account for that.
  • performance is the goal.
    Conceptually, this is basically a set of algorithms that you want your hardware to solve, each one with a respective weight of importance.
    Serial performance is fundamentally limited by the longest path that electrons have to travel in a given clock cycle.
    The way to work around it is to create pipelines, splitting up single operations into multiple smaller operations, and storing intermediate results in memories.
They put a lot of expensive equipment together, much of it made by other companies, and they make the entire chip for companies ordering them.
A list of fabs can be seen at: and basically summarizes all the companies that have fabs.
AMD just gave up this risky part of the business amidst the fabless boom. Sound like a wise move. They then fell more and more away from the state of the art, and moved into more niche areas.
Video 1. SMIC, Explained by Asianometry (2021) Source.
One of the companies that has fabs, which buys machines from companies such as ASML and puts them together in so called "silicon fabs" to make the chips
As the quintessential fabless fab, there is on thing TSMC can never ever do: sell their own design! It must forever remain a fab-only company, that will never compete with its customers. This is highlighted e.g. at from Video "How Nvidia Won Graphics Cards by Asianometry (2021)".
Video 1. How Taiwan Created TSMC by Asianometry (2020) Source. Some points:
  • UCM failed because it focused too much on the internal market, and was shielded from external competition, so it didn't become world leading
  • one of TSMC's great advances was the fabless business model approach.
  • they managed to do large technology transfers from the West to kickstart things off
  • one of their main victories was investing early in CMOS, before it became huge, and winning that market
Basically what register transfer level compiles to in order to achieve a real chip implementation.
After this is done, the final step is place and route.
They can be designed by third parties besides the semiconductor fabrication plants. E.g. Arm Ltd. markets its Artisan Standard Cell Libraries as mentioned e.g. at: This came from a 2004 acquisition:, obviously.
The standard cell library is typically composed of a bunch of versions of somewhat simple gates, e.g.:
  • AND with 2 inputs
  • AND with 3 inputs
  • AND with 4 inputs
  • OR with 2 inputs
  • OR with 3 inputs
and so on.
Each of those gates has to be designed by hand as a 3D structure that can be produced in a given fab.
Simulations are then carried out, and the electric properties of those structures are characterized in a standard way as a bunch of tables of numbers that specify things like:
  • how long it takes for electrons to pass through
  • how much heat it produces
Those are then used in power, performance and area estimates.
Open source ones:
A set of software programs that compile high level register transfer level languages such as Verilog into something that a fab can actually produce. One is reminded of a compiler toolchain but on a lower level.
The most important steps of that include:
The output of this step is another Verilog file, but one that exclusively uses interlinked cell library components.
Given a bunch of interlinked standard cell library elements from the logic synthesis step, actually decide where exactly they are going to go on 2D (stacked 2D) integrated circuit surface.
Sample output format of place and route would be GDSII.
Figure 1. 3D rendering of a GDSII file. Source.
The main ones as of 2020 are:
They apparently even produced a real working small RISC-V chip with the flow, not bad.
Very good channel to learn some basics of semiconductor device fabrication!
Focuses mostly on the semiconductor industry. from Video "SMIC, Explained by Asianometry (2021)" from mentions he is of Chinese ascent, ancestors from Ningbo. Earlier in the same video he mentions he worked on some startups. He doesn't appear to speak perfect Mandarin Chinese anymore though based on pronounciation of Chinese names. gives an abbreviated name "Jon Y".
Video 1. Reflecting on Asianometry in 2022 by Asianometry (2022) Source. Mentions his insane work schedule: 4 hours research in the morning, then day job, then editing and uploading until midnight. Appears to be based in Taipei. Two videos a week. So even at the current 400k subs, he still can't make a living.