Register transfer level (RTL)

The only two truly relevant RTL languages as of 2020 are: Verilog and VHDL. Everything else compiles to those, because that's all that EDA vendors support.

Much like a C compiler abstracts away the CPU assembly to:

increase portability across ISAs
do optimizations that programmers can't feasibly do without going crazy

Compilers for RTL languages such as Verilog and VHDL abstract away the details of the specific semiconductor technology used for those exact same reasons.

The compilers essentially compile the RTL languages into a standard cell library.

Examples of companies that work at this level include:

Intel. Intel also has semiconductor fabrication plants however.
Arm which does not have fabs, and is therefore called a "fabless" company.

Fabless manufacturing

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In the past, most computer designers would have their own fabs.

But once designs started getting very complicated, it started to make sense to separate concerns between designers and fabs.

What this means is that design companies would primarily write register transfer level, then use electronic design automation tools to get a final manufacturable chip, and then send that to the fab.

It is in this point of time that TSMC came along, and benefied and helped establish this trend.

The term "Fabless" could in theory refer to other areas of industry besides the semiconductor industry, but it is mostly used in that context.

Verilog

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Examples under verilog, more details at Verilator.

Verilator

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Verilog simulator that transpiles to C++.

One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.

Some simulation examples under verilog.

First install Verilator. On Ubuntu:

sudo apt install verilator

Tested on Verilator 4.038, Ubuntu 22.04.

Run all examples, which have assertions in them:

cd verilator
make run

File structure is for example:

verilog/counter.v: Verilog file
verilog/counter.cpp: C++ loop which clocks the design and runs tests with assertions on the outputs
verilog/counter.params: gcc compilation flags for this example
verilog/counter_tb.v: Verilog version of the C++ test. Not used by Verilator. Verilator can't actually run out _tb files, because they do in Verilog IO things that we do better from C++ in Verilator, so Verilator didn't bother implementing them. This is a good thing.

Example list:

verilog/negator.v, verilog/negator.cpp: the simplest non-identity combinatorial circuit!
verilog/counter.v, verilog/counter.cpp: sequential hello world. Synchronous active high reset with active high enable signal. Adapted from: www.asic-world.com/verilog/first1.html
verilog/subleq.v, verilog/subleq.cpp: subleq one instruction set computer with separated instruction and data RAMs

Verilator interactive example

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The example under verilog/interactive showcases how to create a simple interactive visual Verilog example using Verilator and SDL.

https://raw.githubusercontent.com/cirosantilli/media/master/verilog-interactive.gif

You could e.g. expand such an example to create a simple (or complex) video game for example if you were insane enough. But please don't waste your time doing that, Ciro Santilli begs you.

The example is also described at: stackoverflow.com/questions/38108243/is-it-possible-to-do-interactive-user-input-and-output-simulation-in-vhdl-or-ver/38174654#38174654

Usage: install dependencies:

sudo apt install libsdl2-dev verilator

then run as either:

make run RUN=and2
make run RUN=move

Tested on Verilator 4.038, Ubuntu 22.04.

File overview:

In those examples, the more interesting application specific logic is delegated to Verilog (e.g.: move game character on map), while boring timing and display matters can be handled by SDL and C++.