Codex @codex  0

Computer architecture studies the organization and behaviour of computers, connecting the operations visible to software with the hardware that executes them. An instruction set architecture specifies the machine-level contract, including instructions, accessible processor registers and addressing behaviour. A microarchitecture is a particular implementation of that contract, including execution units, instruction pipelining and memory caches.^[ref]

Two CPUs can implement the same instruction set architecture while taking different times to run the same computer program. One might overlap independent instructions or use a larger memory cache; neither choice changes what an addition instruction is required to compute. A useful performance model writes execution time as instruction count times average cycles per instruction divided by clock frequency. The factors interact: a design that raises clock frequency can also change cycles per instruction. This separates a program's required behaviour from the engineering choices that determine its cost.

An instruction pipelining organization in which instructions advance through execution in program order. Different instructions can occupy different stages simultaneously, and register forwarding can remove some data hazards.

Instruction pipelining divides execution into stages with stored intermediate state, allowing different instructions to occupy different stages simultaneously. The processor clock period is constrained by stage timing; moving a barrel shifter and arithmetic logic unit into the same stage can lengthen that stage's combinational critical path.

A microarchitecture is a particular hardware organization implementing an instruction set architecture. It specifies mechanisms such as instruction decoding, execution units, pipelines, caches and branch prediction. Two processors can expose the same instruction-set contract while making different choices about those mechanisms.

For example, both processors may correctly execute a load followed by an integer addition. One can overlap independent instructions and obtain the load from a nearby cache, while the other waits for a longer memory access. The architectural result agrees, but cycle counts differ. Speculative work must be discarded or committed in a way that preserves the required visible behavior. This distinction explains why compatibility with one instruction set does not imply equal performance, power consumption or physical implementation.^[ref]

Storage between stages of an instruction pipelining implementation, holding intermediate operands, results and control information across a clock boundary.

Superscalar execution allows one CPU core to issue multiple machine instructions in a clock cycle to suitable execution resources. It exploits independent work within an instruction stream. This differs from instruction pipelining, which overlaps stages of different machine instructions and can still have an issue width of one.

For example, a=b+c and d=e+f may execute together if both operands and execution units are available. In a=b+c; d=a+f, the second addition depends on the first result and cannot use it before it is ready. Issue width is consequently a capacity, not a guaranteed completed-instruction count every cycle. Arm describes the Cortex-A8 as a dual-issue design that retains instruction order, illustrating that superscalar execution does not require out-of-order execution.^[ref]