Past exam of the year 1 of the computer science course of the University of Oxford / 2016 / Digital systems, linear algebra, introduction to formal proof / 1 / c

Use eight parallel 8:1 multiplexers and one shared three-bit binary counter. If $d_{i,j}$ is bit $j$ from sensor $i$, connect $d_{0,j},\dots ,d_{7,j}$ to multiplexer $j$. Connect all selection inputs to the binary counter outputs. Then data line $j$ carries $d_{q,j}$, so all eight data lines belong to the same selected sensor. Send the three counter outputs to the receiver as the address lines as well.

After reset the receiver sees sensors $0,1,\dots ,7,0,\dots$, one per clock period. Sample the data and address only after the binary counter and multiplexers have settled, for example on the opposite clock edge with a sufficiently long clock period. Changing addresses can otherwise cause transient logic hazards. The transmitter uses eleven signal lines, apart from any shared clock or reset connection.