Linear polynomial Updated 2025-07-16
A polynomial of degree 1, i.e. of form .
As of 2020, no one knows how to build the major desktop distros fully from source into the ISO, and especially so in a reproducible build way. Everything is done in build servers somewhere with complicated layers of prebuilds. It's crap.
Non-relativistic quantum mechanics Updated 2025-07-16
The first quantum mechanics theories developed.
Their most popular formulation has been the Schrödinger equation.
NoSQL Updated 2025-07-16
Trinity (nuclear test) Updated 2025-07-16
Plutonium-based.
Its plutonium was produced at Hanford site.
Video 1.
Trinity Test Preparations by AtomicHeritage (2016)
Source. Appears to be a compilation of several videos, presumably each with their own separate LA-UR, though these are not noted. Credited: "Video courtesy of the Los Alamos National Laboratory Archives", TODO how to search that archive online?
Video 2.
Trinity: Getting The Job Done
. Source. Good video, clarifies several interesting technical points:
Turing complete Updated 2025-07-16
A computer model that is as powerful as the most powerful computer model we have: Turing machine!
Turing machine regex tape notation Updated 2025-07-16
Turing machine regex tape notation is Ciro Santilli's made up name for the notation used e.g. at:Most of it is just regular regular expression notation, with a few differences:
  • denotes the right or left edge of the (zero initialized) tape. It is often omitted as we always just assume it is always present on both sides of every regex
  • A, B, C, D and E denotes the current machine state. This is especially common notation in the context of the BB(5) problem
  • < and > next to the state indicate if the head is on top of the left or right element. E.g.:
    11 (01)^n <A 00 (0011)^{n+2}
    indicates that the head A is on top of the last 1 of the last sequence of n 01s to the left of the head.
This notation is very useful, as it helps compress long repeated sequences of Turing machine tape and extract higher level patterns from them, which is how you go about understanding a Turing machine in order to apply Turing machine acceleration.
x86 Paging Tutorial / Page faults Updated 2025-07-16
What if Process 1 tries to access 0x00003000, which is not present?
The hardware notifies the software via a Page Fault Exception.
When an exception happens, the CPU jumps to an address that the OS had previously registered as the fault handler. This is usually done at boot time by the OS.
This could happen for example due to a programming error:
int *is = malloc(1);
is[2] = 1;
but there are cases where it is not a bug, for example in Linux when:
  • the program wants to increase its stack.
    It just tries to accesses a certain byte in a given possible range, and if the OS is happy it adds that page to the process address space, otherwise, it sends a signal to the process.
  • the page was swapped to disk.
    The OS will need to do some work behind the processes back to get the page back into RAM.
    The OS can discover that this is the case based on the contents of the rest of the page table entry, since if the present flag is clear, the other entries of the page table entry are completely left for the OS to to what it wants.
    On Linux for example, when present = 0:
    • if all the fields of the page table entry are 0, invalid address.
    • else, the page has been swapped to disk, and the actual values of those fields encode the position of the page on the disk.
In any case, the OS needs to know which address generated the Page Fault to be able to deal with the problem. This is why the nice IA32 developers set the value of cr2 to that address whenever a Page Fault occurs. The exception handler can then just look into cr2 to get the address.
Why are pages 4 KiB anyways?
There is a trade-off between memory wasted in:
  • page tables
  • extra padding memory within pages
This can be seen with the extreme cases:
  • if the page size were 1 byte:
    • granularity would be great, and the OS would never have to allocate unneeded padding memory
    • but the page table would have 2^32 entries, and take up the entire memory!
  • if the page size were 4 GiB:
    • we would need to swap 4 GiB to disk every time a new process becomes active
    • the page size would be a single entry, so it would take almost no memory at all
x86 designers have found that 4 KiB pages are a good middle ground.
Intuitively we see that the situation is fundamentally different from the Turing machine that halts if and only if the Goldbach conjecture is false because for Collatz the counter example must go off into infinity, while in Goldbach conjecture we can finitely check any failures.
Amazing.
TuxGuitar Updated 2025-07-16
Just use MuseScore instead.
Can import from: MIDI.
Can export to:
Ubuntu 20.04:
sudo apt install tuxguitar tuxguitar-alsa tuxguitar-jsa tuxguitar-oss
tuxguitar-jsa was needed, otherwise no sound: askubuntu.com/questions/457321/tuxguitar-no-sound-in-14-04
Has OK step sequencer non-realtime up/down/left/right guitar based composition interface.
Has chord insertion.
Has bend editor.
Could be more amazing, but it is OK.
A bit limited by being very "guitar oriented". Shows you guitar strings, and you enter offset to each string. So to enter two adjacent notes you need to use two seprate strings and thing about the offsets. If only it had a more piano based interface.
Drum notation is also atrocious, you have to go to the top chord, and use high numbers starting at 36.
x86 Paging Tutorial / PAE Updated 2025-07-16
Physical address extension.
With 32 bits, only 4GB RAM can be addressed.
This started becoming a limitation for large servers, so Intel introduced the PAE mechanism to Pentium Pro.
To relieve the problem, Intel added 4 new address lines, so that 64GB could be addressed.
Page table structure is also altered if PAE is on. The exact way in which it is altered depends on weather PSE is on or off.
PAE is turned on and off via the PAE bit of cr4.
Even if the total addressable memory is 64GB, individual process are still only able to use up to 4GB. The OS can however put different processes on different 4GB chunks.
Twin paradox Updated 2025-07-16
The key question is: why is this not symmetrical?
One answer is: because one of the twin accelerates, and therefore changes inertial frames.
But the better answer is: understand what happens when the stationary twin sends light signals at constant time intervals to each other. When does the travelling twin receives them?
By doing that, we see that "all the extra aging happens immediately when the twin turns around":
  • on the out trip, both twins receive signals at constant intervals
  • when the moving twin turns around and starts to accelerate through different inertial frames, shit happens:
    • the moving twin suddenly notices that the rate of signals from the stationary twin increased. They are getting older faster than us!
    • the stationary twin suddenly notices that the rate of signals from the moving twin decreased. They are getting older slower than us!
  • then when the moving twin reaches the return velocity, both see constant signal rates once again
Figure 1.
Twin paradox illustration with twins sending light signals at regular intervals
. Source.
Another way of understanding it is: you have to make all calculations on a single inertial frame for the entire trip.
Supposing the sibling quickly accelerates out (or magically starts moving at constant speed), travels at constant speed, and quickly accelerates back, and travels at constant speed setup, there are three frames that seem reasonable:
  • the frame of the non-accelerating sibling
  • the outgoing trip of the accelerating sibling
  • the return trip of the accelerating sibling
If you do that, all three calculations give the exact same result, which is reassuring.
Another way to understand it is to do explicit integrations of the acceleration: physics.stackexchange.com/questions/242043/what-is-the-proper-way-to-explain-the-twin-paradox/242044#242044 This is the least insightful however :-)
Bibliography:
The exact format of table entries is fixed by the hardware.
Each page entry can be seen as a struct with many fields.
The page table is then an array of struct.
On this simplified example, the page table entries contain only two fields:
bits   function
-----  -----------------------------------------
20     physical address of the start of the page
1      present flag
so in this example the hardware designers could have chosen the size of the page table to b 21 instead of 32 as we've used so far.
All real page table entries have other fields, notably fields to set pages to read-only for Copy-on-write. This will be explained elsewhere.
It would be impractical to align things at 21 bits since memory is addressable by bytes and not bits. Therefore, even in only 21 bits are needed in this case, hardware designers would probably choose 32 to make access faster, and just reserve bits the remaining bits for later usage. The actual value on x86 is 32 bits.
Here is a screenshot from the Intel manual image "Formats of CR3 and Paging-Structure Entries with 32-Bit Paging" showing the structure of a page table in all its glory: Figure 1. "x86 page entry format".
Figure 1.
x86 page entry format
.
The fields are explained in the manual just after.
Nuclear weapon Updated 2025-07-16
Figure 1.
A weapons-grade ring of electrorefined plutonium, typical of the rings refined at Los Alamos and sent to Rocky Flats for fabrication
. Source. The ring has a purity of 99.96%, weighs 5.3 kg, and is approx 11 cm in diameter. It is enough plutonium for one bomb core. Which city shall we blow up today?
Ciro Santilli is mildly obsessed by nuclear reactions, because they are so quirky. How can a little ball destroy a city? How can putting too much of it together produce criticality and kill people like in the Slotin accident or the Tokaimura criticality accident. It is mind blowing really.
Video 1.
Tour of a nuclear misile silo from the 60's by Arizona Highways TV (2019)
Source.
Video 2.
The Ultimate Guide to Nuclear Weapons by hypohystericalhistory (2022)
Source. Good overall summary. Some interesting points:
Toffoli gate Updated 2025-07-16
For each process, the virtual address space looks like this:
------------------ 2^32 - 1
Stack (grows down)
v v v v v v v v v
------------------

(unmapped)

------------------ Maximum stack size.


(unmapped)


-------------------
mmap
-------------------


(unmapped)


-------------------
^^^^^^^^^^^^^^^^^^^
brk (grows up)
-------------------
BSS
-------------------
Data
-------------------
Text
-------------------

------------------- 0
The kernel maintains a list of pages that belong to each process, and synchronizes that with the paging.
If the program accesses memory that does not belong to it, the kernel handles a page-fault, and decides what to do:
  • if it is above the maximum stack size, allocate those pages to the process
  • otherwise, send a SIGSEGV to the process, which usually kills it
When an ELF file is loaded by the kernel to start a program with the exec system call, the kernel automatically registers text, data, BSS and stack for the program.
The brk and mmap areas can be modified by request of the program through the brk and mmap system calls. But the kernel can also deny the program those areas if there is not enough memory.
brk and mmap can be used to implement malloc, or the so called "heap".
mmap is also used to load dynamically loaded libraries into the program's memory so that it can access and run it.
Calculating exact addresses Things are complicated by:
x86 Paging Tutorial / PSE Updated 2025-07-16
Page size extension.
Allows for pages to be 4M (or 2M if PAE is on) in length instead of 4K.
PSE is turned on and off via the PSE bit of cr4.

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