Ciro Santilli @cirosantilli  40

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Term symbol Updated 2025-07-16

This notation is so confusing! People often don't manage to explain the intuition behind it, why this is an useful notation. When you see Indian university entry exam level memorization classes about this, it makes you want to cry.

The key reason why term symbols matter are Hund's rules, which allow us to predict with some accuracy which electron configurations of those states has more energy than the other.

web.chem.ucsb.edu/~devries/chem218/Term%20symbols.pdf puts it well: electron configuration notation is not specific enough, as each such notation e.g. 1s2 2s2 2p2 contains several options of spins and z angular momentum. And those affect energy.

This is why those symbols are often used when talking about energy differences: they specify more precisely which levels you are talking about.

Basically, each term symbol appears to represent a group of possible electron configurations with a given quantum angular momentum.

We first fix the energy level by saying at which orbital each electron can be (hyperfine structure is ignored). It doesn't even have to be the ground state: we can make some electrons excited at will.

The best thing to learn this is likely to draw out all the possible configurations explicitly, and then understand what is the term symbol for each possible configuration, see e.g. term symbols for carbon ground state.

It also confusing how uppercase letters S, P and D are used, when they do not refer to orbitals s, p and d, but rather to states which have the same angular momentum as individual electrons in those states.

It is also very confusing how extremelly close it looks to spectroscopic notation!

The form of the term symbol is:

^{2 S + 1} L_{J}

The

2 S + 1

can be understood directly as the degeneracy, how many configurations we have in that state.

Atomic Term Symbols by TMP Chem (2015)

Atomic Term Symbols by T. Daniel Crawford (2016)

youtu.be/DAgEmLWpYjs?t=2675 term symbols for carbon ground state

Bibliography:

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Fermentation Updated 2025-07-16

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ATP synthase Updated 2025-07-16

One of the most beautiful molecular machines known!

The first one with such complexity that was uncovered.

The thing rotates like a water wheel for God's sake, except it uses protons instead of water.

The ATP synthase complex is so large that Power, Sex, Suicide by Nick Lane (2006) page 123 contains a cryoEM image of several ATP synthases on small membrane vesicles, this is the paper: pubs.acs.org/doi/abs/10.1021/bi00437a031# under a fucking paywall.

ATP synthase in action by HarvardX (2017)

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ARM Cortex-M0+ Updated 2025-07-16

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Anomalous magnetic dipole moment of the electron Updated 2025-07-16

Richard Feynman Quantum Electrodynamics Lecture at University of Auckland (1979) mentions it several times.

This was one of the first two great successes of quantum electrodynamics, the other one being the Lamb shift.

In youtu.be/UKbp85zpdcY?t=52 from freeman Dyson Web of Stories interview (1998) Dyson mentions that the original key experiment was from Kusch and Foley from Columbia University, and that in 1948, Julian Schwinger reached the correct value from his calculations.

Apparently first published at The Magnetic Moment of the Electron by Kusch and Foley (1948).

Bibliography:

www.youtube.com/watch?v=Ix-3LQhElvU Anomalous Magnetic Moment Of The Electron | One Loop Quantum Correction | Quantum Electrodynamics by Dietterich Labs (2019)

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Radeon Updated 2025-07-16

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Advanced quantum field theory lecture by Tobias Osborne (2017) / Lecture 2 Updated 2025-07-16

www.youtube.com/watch?v=hapYr6rX4JM&list=PLDfPUNusx1ErSu1JDVV1KKGQkJQCkzL9u&index=2

Gaussian path integrals.

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Classification of 2-transitive groups Updated 2025-07-16

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Yang-Mills existence and mass gap Updated 2025-07-16

www.youtube.com/watch?v=-_qNKbwM_eE Unsolved: Yang-Mills existence and mass gap by J Knudsen (2019). Gives 10 key points, but the truly hard ones are too quick. He knows the thing though.

Yang-Mills 1 by David Metzler (2011)

Playlist: www.youtube.com/watch?v=j3fsPHnrgLg&list=PL613A31A706529585&index=13

A bit disappointing, too high level, with very few nuggests that are not Googleable withing 5 minutes.

Breakdown:

1 www.youtube.com/watch?v=j3fsPHnrgLg: too basic
2 www.youtube.com/watch?v=br6OxCLyqAI?t=569: mentions groups of Lie type in the context of classification of finite simple groups. Each group has a little diagram.
3 youtu.be/1baiIxKKQlQ?list=PL613A31A706529585&t=728 the original example of a local symmetry was general relativity, and that in that context it can be clearly seen that the local symmetry is what causes "forces" to appear
- youtu.be/1baiIxKKQlQ?list=PL613A31A706529585&t=933 local symmetry gives a conserved current. In the case of electromagnetism, this is electrical current. This was the only worthwhile thing he sad to 2021 Ciro. Summarized at: local symmetries of the Lagrangian imply conserved currents.
4 youtu.be/5ljKcWm7hoU?list=PL613A31A706529585&t=427 electromagnetism has both a global symmetry (special relativity) but also local symmetry, which leads to the conservation of charge current and forces.
lecture 3 properly defines a local symmetry in terms of the context of the lagrangian density, and explains that the conservation of currents there is basically the statement of Noether's theorem in that context.

Millennium Prize Problem: Yang Mills Theory by David Gross (2018)

Source. 2 hour talk at the Kavli Institute for Theoretical Physics. Too mathematical, 2021 Ciro can't make much out of it.

Lorenzo Sadun on the "Yang-Mills and Mass Gap" Millennium problem

. Source. Unknown year. He almost gets there, he's good. Just needed to be a little bit deeper.

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x86 Paging Tutorial / Basic TLB operation Updated 2025-07-16

After a translation between linear and physical address happens, it is stored on the TLB. For example, a 4 entry TLB starts in the following state:

  valid  linear  physical
  -----  ------  --------
> 0      00000   00000
  0      00000   00000
  0      00000   00000
  0      00000   00000

The > indicates the current entry to be replaced.

And after a page linear address 00003 is translated to a physical address 00005, the TLB becomes:

  valid  linear  physical
  -----  ------  --------
  1      00003   00005
> 0      00000   00000
  0      00000   00000
  0      00000   00000

and after a second translation of 00007 to 00009 it becomes:

  valid  linear  physical
  -----  ------  --------
  1      00003   00005
  1      00007   00009
> 0      00000   00000
  0      00000   00000

Now if 00003 needs to be translated again, hardware first looks up the TLB and finds out its address with a single RAM access 00003 --> 00005.

Of course, 00000 is not on the TLB since no valid entry contains 00000 as a key.

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x86 Paging Tutorial / TLB replacement policy Updated 2025-07-16

When TLB is filled up, older addresses are overwritten. Just like CPU cache, the replacement policy is a potentially complex operation, but a simple and reasonable heuristic is to remove the least recently used entry (LRU).

With LRU, starting from state:

  valid  linear  physical
  -----  ------  --------
> 1      00003   00005
  1      00007   00009
  1      00009   00001
  1      0000B   00003

adding 0000D -> 0000A would give:

  valid  linear  physical
  -----  ------  --------
  1      0000D   0000A
> 1      00007   00009
  1      00009   00001
  1      0000B   00003

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x86 Paging Tutorial / CAM Updated 2025-07-16

Using the TLB makes translation faster, because the initial translation takes one access per TLB level, which means 2 on a simple 32 bit scheme, but 3 or 4 on 64 bit architectures.

The TLB is usually implemented as an expensive type of RAM called content-addressable memory (CAM). CAM implements an associative map on hardware, that is, a structure that given a key (linear address), retrieves a value.

Mappings could also be implemented on RAM addresses, but CAM mappings may required much less entries than a RAM mapping.

For example, a map in which:

both keys and values have 20 bits (the case of a simple paging schemes)
at most 4 values need to be stored at each time

could be stored in a TLB with 4 entries:

linear  physical
------  --------
00000   00001
00001   00010
00010   00011
FFFFF   00000

However, to implement this with RAM, it would be necessary to have 2^20 addresses:

linear  physical
------  --------
00000   00001
00001   00010
00010   00011
... (from 00011 to FFFFE)
FFFFF   00000

which would be even more expensive than using a TLB.

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x86 Paging Tutorial / Invalidating TLB entries Updated 2025-07-16

When the process changes, cr3 change to point to the page table of the new current process.

This creates a problem: the TLB is now filled with a bunch of cached entries for the old process.

A simple and naive solution would be to completely invalidate the TLB whenever the cr3 changes.

However, this is would not be very efficient, because it often happens that we switch back to process 1 before process 2 has completely used up the entire TLB cache entries.

The solution for this is to use so called "Address Space Identifiers" (ASID) as mentioned in sources such as:

Basically, the OS assigns a different ASID for each process, and then TLB entries are automatically also tagged with that ASID. This way when the process makes an access, the TLB can determine if a hit is actually for the current process, or if it is an old address coincidence with another process.

The x86 also offers the invlpg instruction which explicitly invalidates a single TLB entry. Other architectures offer even more instructions to invalidated TLB entries, such as invalidating all entries on a given range.

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x86 Paging Tutorial / ARM Updated 2025-07-16

Information about ARM paging can be found at: cirosantilli.com/linux-kernel-module-cheat#arm-paging

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x86 Paging Tutorial / Play with physical addresses in Linux Updated 2025-07-16

Convert virtual addresses to physical from user space with /proc/<pid>/pagemap and from kernel space with virt_to_phys:

Dump all page tables from userspace with /proc/<pid>/maps and /proc/<pid>/pagemap:

Read and write physical addresses from userspace with /dev/mem:

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x86 Paging Tutorial / Kernel vs process memory layout Updated 2025-07-16

The Linux Kernel reserves two zones of virtual memory:

one for kernel memory
one for programs

The exact split is configured by CONFIG_VMSPLIT_.... By default:

on 32-bit:

the bottom 3/4 is program space: 00000000 to BFFFFFFF

the top 1/4 is kernel memory: C0000000 to FFFFFFFF, like this:

------------------ FFFFFFFF
Kernel
------------------ C0000000
------------------ BFFFFFFF


Process


------------------ 00000000

on 64-bit: currently only 48-bits are actually used, split into two equally sized disjoint spaces. The Linux kernel just assigns:
- the bottom part to processes 00000000 00000000 to 008FFFFF FFFFFFFF
- the top part to the kernel: FFFF8000 00000000 to FFFFFFFF FFFFFFFF, like this:
  ------------------ FFFFFFFF Kernel ------------------ C0000000 (not addressable) ------------------ BFFFFFFF Process ------------------ 00000000

Kernel memory is also paged.

In previous versions, the paging was continuous, but with HIGHMEM this changed.

There is no clear physical memory split: stackoverflow.com/questions/30471742/physical-memory-userspace-kernel-split-on-linux-x86-64

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x86 Paging Tutorial / Process memory layout Updated 2025-07-16

For each process, the virtual address space looks like this:

------------------ 2^32 - 1
Stack (grows down)
v v v v v v v v v
------------------

(unmapped)

------------------ Maximum stack size.


(unmapped)


-------------------
mmap
-------------------


(unmapped)


-------------------
^^^^^^^^^^^^^^^^^^^
brk (grows up)
-------------------
BSS
-------------------
Data
-------------------
Text
-------------------

------------------- 0

The kernel maintains a list of pages that belong to each process, and synchronizes that with the paging.

If the program accesses memory that does not belong to it, the kernel handles a page-fault, and decides what to do:

if it is above the maximum stack size, allocate those pages to the process
otherwise, send a SIGSEGV to the process, which usually kills it

When an ELF file is loaded by the kernel to start a program with the exec system call, the kernel automatically registers text, data, BSS and stack for the program.

The brk and mmap areas can be modified by request of the program through the brk and mmap system calls. But the kernel can also deny the program those areas if there is not enough memory.

brk and mmap can be used to implement malloc, or the so called "heap".

mmap is also used to load dynamically loaded libraries into the program's memory so that it can access and run it.

Stack allocation: stackoverflow.com/questions/17671423/stack-allocation-for-process

Calculating exact addresses Things are complicated by:

Address Space Layout Randomization.
the fact that environment variables, CLI arguments, and some ELF header data take up initial stack space: unix.stackexchange.com/questions/145557/how-does-stack-allocation-work-in-linux/239323#239323

Why the text does not start at 0: stackoverflow.com/questions/14795164/why-do-linux-program-text-sections-start-at-0x0804800-and-stack-tops-start-at-0

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x86 Paging Tutorial / Copy-on-write Updated 2025-07-16

en.wikipedia.org/wiki/Copy-on-write

Besides a missing page, a very common source of page faults is copy-on-write (COW).

Page tables have extra flags that allow the OS to mark a page a read-only.

Those page faults only happen when a process tries to write to the page, and not read from it.

When Linux forks a process:

instead of copying all the pages, which is unnecessarily costly, it makes the page tables of the two process point to the same physical address.
it marks those linear addresses as read-only
whenever one of the processes tries to write to a page, the makes a copy of the physical memory, and updates the pages of the two process to point to the two different physical addresses

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x86 Paging Tutorial / Linux source tree Updated 2025-07-16

In v4.2, look under arch/x86/:

include/asm/pgtable*
include/asm/page*
mm/pgtable*
mm/page*

There seems to be no structs defined to represent the pages, only macros: include/asm/page_types.h is specially interesting. Excerpt:

#define _PAGE_BIT_PRESENT   0   /* is present */
#define _PAGE_BIT_RW        1   /* writeable */
#define _PAGE_BIT_USER      2   /* userspace addressable */
#define _PAGE_BIT_PWT       3   /* page write through */

arch/x86/include/uapi/asm/processor-flags.h defines CR0, and in particular the PG bit position:

#define X86_CR0_PG_BIT      31 /* Paging */

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x86 Paging Tutorial / Single level paging scheme visualization Updated 2025-07-16

This is how the memory could look like in a single level paging scheme:

Links   Data                    Physical address

      +-----------------------+ 2^32 - 1
      |                       |
      .                       .
      |                       |
      +-----------------------+ page0 + 4k
      | data of page 0        |
+---->+-----------------------+ page0
|     |                       |
|     .                       .
|     |                       |
|     +-----------------------+ pageN + 4k
|     | data of page N        |
|  +->+-----------------------+ pageN
|  |  |                       |
|  |  .                       .
|  |  |                       |
|  |  +-----------------------+ CR3 + 2^20 * 4
|  +--| entry[2^20-1] = pageN |
|     +-----------------------+ CR3 + 2^20 - 1 * 4
|     |                       |
|     .    many entires       .
|     |                       |
|     +-----------------------+ CR3 + 2 * 4
|  +--| entry[1] = page1      |
|  |  +-----------------------+ CR3 + 1 * 4
+-----| entry[0] = page0      |
   |  +-----------------------+ <--- CR3
   |  |                       |
   |  .                       .
   |  |                       |
   |  +-----------------------+ page1 + 4k
   |  | data of page 1        |
   +->+-----------------------+ page1
      |                       |
      .                       .
      |                       |
      +-----------------------+  0

Notice that:

the CR3 register points to the first entry of the page table
the page table is just a large array with 2^20 page table entries
each entry is 4 bytes big, so the array takes up 4 MiB
each page table contains the physical address a page
each page is a 4 KiB aligned 4 KiB chunk of memory that user processes may use
we have 2^20 table entries. Since each page is 4 KiB == 2^12, this covers the whole 4 GiB (2^32) of 32-bit memory

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