Ciro Santilli @cirosantilli 40

The first quantum mechanics theories developed.

Their most popular formulation has been the Schrödinger equation.

Physical address extension.

With 32 bits, only 4GB RAM can be addressed.

This started becoming a limitation for large servers, so Intel introduced the PAE mechanism to Pentium Pro.

To relieve the problem, Intel added 4 new address lines, so that 64GB could be addressed.

Page table structure is also altered if PAE is on. The exact way in which it is altered depends on weather PSE is on or off.

PAE is turned on and off via the PAE bit of cr4.

Even if the total addressable memory is 64GB, individual process are still only able to use up to 4GB. The OS can however put different processes on different 4GB chunks.

Why are pages 4 KiB anyways?

There is a trade-off between memory wasted in:

This can be seen with the extreme cases:

x86 designers have found that 4 KiB pages are a good middle ground.

On Urban Dictionary: www.urbandictionary.com/define.php?term=no%20pun%20intended

www.urbandictionary.com/define.php?term=turd%20polishing on Urban Dictionary.

Ciro Santilli learned this expression from Angry Video Game Nerd.

Page size extension.

Allows for pages to be 4M (or 2M if PAE is on) in length instead of 4K.

PSE is turned on and off via the PSE bit of cr4.

Marc Verdiell is a French electrical engineer born in 1963 or 1964^[ref] and best known for being the creator and host of the CuriousMarc YouTube channel where he does mind blowing repairs and reverse engineering of vintage computers and other electronic equipment.

Marc sold his company LightLogic, an optoelectronics company he founded, to Intel in April 2001. This was just after the dot-com crash, but Intel apparently still correctly believed that the networking and the Internet would continue to grow and was investing in the area. His associate Frank Shum sued claiming he should be credited for some of the inventions sold but lost and Marc got it all.^{[ref][ref][ref]}. Marc was then almost immediately appointed an Intel fellow at the extremelly early age of 37, and then stayed for a few years at Intel until 2006 according to his LinkedIn.^[ref][ref]

Marc's LinkedIn profile: www.linkedin.com/in/marc-verdiell-9742795/

Marc's full name is actualy Jean-Marc Verdiell, but Ciro Santilli remembers there was one YouTube video where he mentions he gave up on "Jean" partly because anglophones would murder its pronounciation all the time.

Marc's PhD thesis is listed at: theses.fr/1990PA112048 and it is entitled:which is translated into English as:but the full text is not available online.

Marc has reached out to us and requested that some personal information be removed from this article, to which we complied.

The Translation Lookahead Buffer (TLB) is a cache for paging addresses.

Since it is a cache, it shares many of the design issues of the CPU cache, such as associativity level.

This section shall describe a simplified fully associative TLB with 4 single address entries. Note that like other caches, real TLBs are not usually fully associative.

In your normal 2020 broken educational system, it is the first time at which students get an official chance to learn something advanced, and possibly prepare to go venture into the PhD desert.