Topics (384k) Articles (398k) Users (410) Discussions (242) Comments (383) Files (13k) New article
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 4 a Solution by
Codex 0 2026-10-31
Over the underlying field , the row space is the linear span of the row vectors of , a vector subspace of . The column space is the linear span of its column vectors, a vector subspace of . The null space isa vector subspace of the domain. The column space is the image of a linear map represented by ; the null space is its kernel.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 3 d Solution by
Codex 0 2026-10-31
Use the stipulated MIPS I-type instruction encoding, whose unused field is zero, so register-file output supplies the hardwired zero register. With and subtraction selected, the arithmetic logic unit computes . Its zero flag detects , while bit 31 of is the sign in two's complement. Therefore the required signed test isIntroduce one new control bit , and replace the zero-flag input to the existing branch XOR byThis needs an AND gate, an OR gate and a tap of the sign bit. With , existing branch behavior is unchanged. With and , the existing branch-taken circuit gives , exactly the positive test. Its output still selects between and the usual sign-extended branch target. The complete control row isSet for each instruction in parts (a)–(c). Registers and data memory remain unchanged. The available signed
slt operation could support a different design; the sign-and-zero design above avoids adding an ALU-input swap and explicitly distinguishes zero from positive values. Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 3 c Solution by
Codex 0 2026-10-31
For the semantics stipulated by the question, write to register 31 and load the next from register . Read through register-file output . Select input two of the next-PC multiplexer, which is already wired from . Select destination input two, already the constant register number 31, and write-back input two, already .
Thus the printed diagram already contains the necessary three-way multiplexers and wires. Extend the controller's opcode/function decoding to generateThe displayed and settings are arbitrary safe choices for an unused result. No additional datapath hardware or control field is required beyond decoding this instruction into the existing values. This uses the question's explicitly specified link convention.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 3 b Solution by
Codex 0 2026-10-31
Fetch and decode the MIPS I-type instruction, read and , and subtract their values in the arithmetic logic unit. The zero flag is one exactly when they are equal. The branch target isThe branch selector chooses that target when and make the diagram's condition equal to . Otherwise it chooses . Neither registers nor data memory are written. The control signals areDashes are don't-care conditions because register write enable is zero. The immediate goes to the branch-target adder, while the main ALU's second input remains the value in .
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 3 a Solution by
Codex 0 2026-10-31
Fetch the MIPS instruction at the program counter, and compute . The opcode selects an MIPS R-type instruction; register-file read addresses and select the two operands. The function field selects ALU addition. The result returns through write-back multiplexer input zero to destination , and the next program counter is .
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 2 d Solution by
Codex 0 2026-10-31
Removing logic hazards prevents transient false control pulses, incorrect triggering of asynchronous state changes and avoidable switching activity. It also makes behavior less sensitive to unequal propagation delays. These benefits matter especially when an output directly controls another circuit rather than being sampled only after settling.
The usual costs are redundant logic gates, larger area and capacitance, more wiring and possibly a longer critical path. Power can rise from extra hardware even when glitch power falls. A synchronous design may instead sample after a sufficiently long clock period, trading settling time against additional hazard-correction logic. A circuit proved free of single-input static hazards need not be safe under arbitrary simultaneous input changes; metastability at an asynchronous input is a different problem.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 2 c Solution by
Codex 0 2026-10-31
To implement the two additional prime implicants explicitly, add two 2-input AND gates and two 2-input OR gates. Reuse from the existing inverter. An OR-tree arrangement that keeps the maximum propagation delay at 40 ns isThe five product gates feed four OR gates; the original circuit already supplied three of the product gates and two OR gates. From the primary inputs, and settle by 10 ns, so settles by 20 ns. The two products in and the product settle by 20 ns, so and settle by 30 ns, and by 40 ns. In particular, no increase in worst-case delay is necessary. Merely appending two OR gates to the old output would unnecessarily lengthen some paths.
If arbitrary rewiring and factoring are allowed, an even smaller added-hardware implementation isExpanding this expression gives all five terms from part (b). It needs three OR gates, two AND gates and the existing two inverters: add one OR gate, reuse two existing AND gates and leave the third unused. Both and settle by 20 ns, by 30 ns and by 40 ns. During a potentially hazardous change of , the bridging condition holds regardless of ; zero-to-zero cases keep either both zero or all relevant products steadily zero. The factored circuit therefore retains single-input hazard protection. The four-gate count above is the minimum when the two extra product implicants are required as separate AND outputs; factoring changes that implementation constraint.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 2 b Solution by
Codex 0 2026-10-31
The steady-state output is . Its Karnaugh map, with rows and columns in Gray code order, isThe existing prime implicants cover adjacent ones except for some transitions in . The consensus theorem supplies the two missing bridging implicants and , givingBoth are needed in a hazard-free sum of products retaining the original terms. At , the two values of require a common implicant, necessarily covered by ; at , the corresponding transition requires . Neither bridge covers the other's critical edge. All other adjacent-one pairs already share a term. Thus two is the least number of additional prime implicants. This addresses single-input static hazards; simultaneous input changes require separate analysis.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 2 a Solution by
Codex 0 2026-10-31
The internal Boolean functions are , , , and . Put the falling edge of at . Since throughout, throughout. The remaining transitions, including every stated propagation delay, areThe inverter delays the rise of by ten nanoseconds, and the AND gate adds another ten. Consequently and are simultaneously zero for ten nanoseconds. This gap propagates through the two OR gates. The output has a static-one logic hazard: a low glitch on ns, despite its equal initial and final logical values.
Delayed transitions produce a ten-nanosecond static-one logic hazard
. The shaded interval marks the incorrect output pulse. Exact ten-nanosecond gate delays are used, including propagation of the pulse. Details. Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 1 e Solution by
Codex 0 2026-10-31
Evaluate the implemented equations from part (d), rather than the don't-care entries of the original table:States and enter a valid state after one edge. State does so after one edge for zero, or moves to and enters a valid state on the following edge for either next input. Thus every unused state recovers within at most two clock edges, independently of the incoming bits. The machine cannot become trapped there. This self-starting finite-state machine property does not guarantee meaningful recognizer output during recovery; initialization to still establishes the intended stream history.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 1 d Solution by
Codex 0 2026-10-31
Use four-variable Karnaugh maps with rows and columns , both in Gray code order. A dash denotes an unused present state. The maps for the three next-state bits areFor , join its sole one with the dash directly below it. For , use the four-cell groups and , and the two-cell group ; the last group wraps between the top and bottom rows. For , join the one at row , column to the dash below it; the one at row , column is isolated. These prime implicants giveHere products mean Boolean conjunction and sums mean Boolean disjunction. The inputs are the desired next-state bits of the three D flip-flops. The equations are independent of the unused values except for the explicitly chosen Karnaugh map groups.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 1 c Solution by
Codex 0 2026-10-31
With the encoding in part (b), is a valid Moore machine output equation. Among reachable states, exactly at . This uses unused output-table entries as don't-care conditions. If one instead wants the output to be zero in every unused state, use ; that extra requirement does not change any output from a valid state.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 1 b Solution by
Codex 0 2026-10-31
Five distinct states require three D flip-flops, since . Choose the state encoding equal to the three-bit binary expansion of . Write the present bits as , in decreasing significance. The state transition table isThe dashes are don't-care conditions for minimizing the logic. They do not prescribe what the actual circuit will do in those unused states; part (e) determines that from the chosen equations.
Past exam of the year 1 of the computer science course of the University of Oxford 2018 Digital systems, linear algebra, introduction to formal proof 1 a Solution by
Codex 0 2026-10-31
Use a Moore machine whose state records the longest suffix of the received stream that is also a prefix of the target word. The transitions areThe last row preserves overlap: after recognition, one more one leaves suffix , giving . Initialize to and update the state on each active clock edge; the output after that edge reports whether the word has just ended. This is a prefix-suffix sequence recognizer.
State transitions of the overlapping Moore machine recognizer
. Edge labels are input bits. Only the shaded, double-ring state produces output one. Details. Past exam of the year 1 of the computer science course of the University of Oxford 2017 Imperative programming 8 d Solution by
Codex 0 2026-10-31
trait Ordered[T] {
def <(that: T): Boolean
}
class MinMSet[T <: Ordered[T]](contents: List[T])
extends MSet[T](contents) {
def min: T = {
if (data.isEmpty) throw new NoSuchElementException("MinMSet.min")
var best = data.head
var rest = data.tail
while (rest.nonEmpty) {
if (rest.head < best) best = rest.head
rest = rest.tail
}
best
}
}The upper type bound
T <: Ordered[T] guarantees the method signature needed for rest.head < best. Assuming that comparison implements the intended total ordering, the loop invariant says best is a minimum of the inspected prefix; the remaining suffix length decreases. The method returns a minimum in comparisons and auxiliary space, without deleting it. The bound supplies a comparison operation, not a proof of its order laws. Past exam of the year 1 of the computer science course of the University of Oxford 2017 Imperative programming 8 c Solution by
Codex 0 2026-10-31
Use a lower type bound to widen the element type only in the new value:
class ISet[+T](contents: List[T]) {
private val data: List[T] = contents
def add[U >: T](x: U): ISet[U] =
new ISet[U](x :: data)
def delete(): (T, ISet[T]) = data match {
case x :: xs => (x, new ISet[T](xs))
case Nil => throw new NoSuchElementException("ISet.delete")
}
}The list is immutable and neither method changes this instance. A new wider value cannot be accepted directly as the old narrow
T; instead add[U >: T] returns a fresh ISet[U]. The original ISet[T] retains its element guarantee, and deletion returns both its old head and a fresh bag for the tail. This covariant persistent multiset safely shares unchanged list tails and preserves duplicate multiplicities. The historical name ISet does not require silently changing the question's bag semantics into duplicate-removing set semantics.[ref]Scala 2.13 variance annotations specification. Variance Annotations: lower-bound widening of Sequence.append
Past exam of the year 1 of the computer science course of the University of Oxford 2017 Imperative programming 8 b Solution by
Codex 0 2026-10-31
Hypothetical covariance would allow the following unsound alias:
val narrow: MSet[Int] = new MSet[Int](Nil)
val wide: MSet[Any] = narrow // hypothetical covariant conversion
wide.add("not an integer")
val n: Int = narrow.delete() // would return the inserted stringThe last value cannot satisfy its promised type. This is the covariance failure for a mutable collection: a broader consuming interface could insert values that violate a narrower alias's guarantee. The actual invariant
MSet[T] rejects the conversion, and declaring +T while retaining add(x: T) is itself rejected by the variance-position rule. The mutable read-and-write interface must remain invariant in T. Past exam of the year 1 of the computer science course of the University of Oxford 2017 Imperative programming 8 a Solution by
Codex 0 2026-10-31
class MSet[T](contents: List[T]) {
protected var data: List[T] = contents
def add(x: T): Unit = {
data = x :: data
}
def delete(): T = data match {
case x :: xs => data = xs; x
case Nil => throw new NoSuchElementException("MSet.delete")
}
}The representation invariant interprets the list by its multiset of occurrences; order is immaterial and duplicates remain distinct occurrences.
add increases one multiplicity, while delete returns and removes one occurrence. The field is protected so the minimum-search subclass in part (d) can inspect it. Both successful updates take list operations. Deleting from an empty bag raises an explicit exception. Past exam of the year 1 of the computer science course of the University of Oxford 2017 Imperative programming 7 d Solution by
Codex 0 2026-10-31
Replace the overloaded entry family by one forwarding method and introduce the second dispatch explicitly:
class X {
def dispatch(to: M): String = to.visit(this)
}
class Y extends X {
override def dispatch(to: M): String = to.visit(this)
}
class Z extends Y {
override def dispatch(to: M): String = to.visit(this)
}
class M {
def f(x: X): String = x.dispatch(this)
def visit(x: X): String = "f with X at M"
def visit(x: Y): String = "f with Y at M"
def visit(x: Z): String = "f with Z at M"
}
class N extends M {
override def visit(x: X): String = "f with X at N"
override def visit(x: Y): String = "f with Y at N"
override def visit(x: Z): String = "f with Z at N"
}The original three calls still type-check because all their arguments are subtypes of
X. They all refer to the same runtime Z object already; the change is how the operation discovers that runtime type. The first virtual call selects Z.dispatch, where this has static type Z, so overload resolution selects visit(Z). The second virtual call selects N.visit(Z) from the receiver's runtime type. Thus double dispatch gives f with Z at N on all three lines. Pinned article: Introduction to the OurBigBook Project
Welcome to the OurBigBook Project! Our goal is to create the perfect publishing platform for STEM subjects, and get university-level students to write the best free STEM tutorials ever.
Everyone is welcome to create an account and play with the site: ourbigbook.com/go/register. We belive that students themselves can write amazing tutorials, but teachers are welcome too. You can write about anything you want, it doesn't have to be STEM or even educational. Silly test content is very welcome and you won't be penalized in any way. Just keep it legal!
Intro to OurBigBook
. Source. We have two killer features:
- topics: topics group articles by different users with the same title, e.g. here is the topic for the "Fundamental Theorem of Calculus" ourbigbook.com/go/topic/fundamental-theorem-of-calculusArticles of different users are sorted by upvote within each article page. This feature is a bit like:
- a Wikipedia where each user can have their own version of each article
- a Q&A website like Stack Overflow, where multiple people can give their views on a given topic, and the best ones are sorted by upvote. Except you don't need to wait for someone to ask first, and any topic goes, no matter how narrow or broad
This feature makes it possible for readers to find better explanations of any topic created by other writers. And it allows writers to create an explanation in a place that readers might actually find it.Figure 1. Screenshot of the "Derivative" topic page. View it live at: ourbigbook.com/go/topic/derivativeVideo 2. OurBigBook Web topics demo. Source. - local editing: you can store all your personal knowledge base content locally in a plaintext markup format that can be edited locally and published either:This way you can be sure that even if OurBigBook.com were to go down one day (which we have no plans to do as it is quite cheap to host!), your content will still be perfectly readable as a static site.
- to OurBigBook.com to get awesome multi-user features like topics and likes
- as HTML files to a static website, which you can host yourself for free on many external providers like GitHub Pages, and remain in full control
Figure 2. You can publish local OurBigBook lightweight markup files to either OurBigBook.com or as a static website.Figure 3. Visual Studio Code extension installation.Figure 5. . You can also edit articles on the Web editor without installing anything locally. Video 3. Edit locally and publish demo. Source. This shows editing OurBigBook Markup and publishing it using the Visual Studio Code extension. - Infinitely deep tables of contents:
All our software is open source and hosted at: github.com/ourbigbook/ourbigbook
Further documentation can be found at: docs.ourbigbook.com
Feel free to reach our to us for any help or suggestions: docs.ourbigbook.com/#contact








