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Incoming links: MIPS architecture
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4224.pdf. The original nine-page cover identifies the Preliminary Examination in Computer Science, Trinity Term 2014, Friday 20 June. Questions 1–3 cover digital counters, the MIPS architecture and file systems; Questions 4–6 cover linear algebra; Questions 7–8 use the supplied natural deduction rules in Figures 1–3 on printed page 9. MIPS instruction 2026-10-31
An instruction in the MIPS architecture, with a specified binary encoding and architectural effect. Educational datapaths often simplify details such as branch delay slots; instruction behavior in a particular circuit must follow that circuit's stated specification. MIPS R-type instructions use register and function fields; MIPS I-type instructions use an immediate field as well as register fields.
MIPS zero register 2026-10-31
Register zero in the MIPS architecture reads as zero and discards writes. An implementation can omit its data storage, hardwire its read output to zero and suppress its write selection. This property permits using zero as a write-suppression destination without changing the visible register values.
A MIPS R-type instruction has the 32-bit instruction encodingFor
add $x,$y,$z, the processor register indices are , and , while . The main opcode selects the R-type family and the function field selects addition. The register file reads its two operands from instruction bits 25:21 and 20:16. In the original datapath, RegDst=1 selects bits 15:11 as the destination, ALUSrc=0 selects the second register file output, and ALUFunc=ADD makes the arithmetic logic unit add its inputs. The result returns to wdata; RegWrite=1 writes it to at the active clock edge. The zero output is irrelevant here.[ref]Digital systems, linear algebra, introduction to formal proof examination paper by the University of Oxford (2014). Question 1 datapath, printed page 2: the input-0 and input-1 multiplexer labels determine these control polarities
A MIPS I-type instruction instead has the instruction encodingFor
addi $x,$y,n, , , and the low sixteen bits contain the immediate operand. The register file supplies to the first arithmetic logic unit input. Set RegDst=0 to select bits 20:16 for the destination, and ALUSrc=1 to select the extended immediate operand for the second input. The opcode directly requests addition, so ALUFunc=ADD and RegWrite=1. The second register file read is unused. The returned result is written into .The sign extension circuit retains the low sixteen bits and copies bit 15 into all sixteen new high positions:Thus sign extension preserves the signed two's complement value:
0x7fff becomes 0x00007fff, whereas 0x8000 becomes 0xffff8000. For both instructions, the architectural result above assumes no signed overflow; the full MIPS architecture specifies an overflow exception, which is outside this simplified datapath.Use byte addresses, so adjacent 32-bit array elements are four bytes apart. The following MIPS instructions include harmless
sll $zero,$zero,0 instructions in every branch delay slot; the second load is followed by another independent instruction before its value is consumed, also accommodating an early MIPS architecture with a load-use delay. All mnemonics here denote individual machine instructions. beq $t3,$zero,done # n=0: do not access any array
sll $zero,$zero,0
loop:
lw $t4,0($t0) # current a element
lw $t5,0($t1) # current b element
addiu $t0,$t0,4 # advance a; also separates lw from its use
subu $t6,$t4,$t5 # current difference, modulo 2^32
sw $t6,0($t2) # store current c element
addiu $t1,$t1,4
addiu $t2,$t2,4
addiu $t3,$t3,-1 # one fewer element remains
bne $t3,$zero,loop
sll $zero,$zero,0
done:A loop invariant at the head of the loop, after completed iterations, is that the three addresses point to elements , the count is , and every output element before equals the corresponding difference. One iteration reads element , stores its difference and advances to , preserving the loop invariant. The remaining count is a nonnegative loop variant decreasing by one, so the loop ends with .
The code uses
subu to avoid signed-overflow traps: the suffix does not restrict the operands to unsigned values. Its precise result isFor representable signed differences this is exactly . If trapping signed arithmetic is required instead, use sub and assume all differences are representable. The arrays must occupy valid word-aligned storage with no address wrap; the usual separate output array avoids overwriting unread inputs.In the pictured single-cycle MIPS architecture,
RegDst selects the write address of the register file: zero selects instruction bits , the rt field used by a load; one selects bits , the rd field used by an MIPS R-type instruction. RegWrite enables the clocked write to the selected processor register.ALUSrc selects the second ALU input: zero uses the second register file read output, while one uses the sign-extended 16-bit immediate field. The zero signal is produced by the ALU, rather than being an opcode-decoder output: it is one exactly when the ALU result is zero. During beq, the ALU subtracts its operands, so zero tests equality. The diagram combines it with Branch to select the branch target instead of .For
add, select rd and the arithmetic logic unit result. For sw, select destination zero while retaining the memory-store controls and source-register reads. For jal, select register 31 and the return-address data. These are the same actual register writes as before, with sw using destination zero in place of disabling RegWrite. Return value 2026-10-31
The result a called procedure supplies to its caller on returning. A calling convention specifies the processor register or memory location carrying it, separately from the return address, which identifies where execution resumes. In the elementary MIPS architecture convention, an integer result is placed in
$v0, while $ra carries the return address.