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An analog switch uses a control signal to connect or disconnect an analog signal path. The control chooses the conducting state; the transmitted electric potential difference is not restricted to a binary logic value. Real devices have finite analog switch on-resistance, leakage and parasitic capacitance. The primary tutorial describes a bilateral CMOS switch formed from complementary transistors.^[ref]

For an original loading example, connect an ideal $1\mathrm{V}$ source through a stipulated $100\Omega$ on-resistance to a $10\mathrm{k\Omega }$ load. The output isThe closed switch therefore changes the amplitude even before any switching transient is considered. This is a chosen resistor model, not a specification for a particular part. Variation of on-resistance with signal level can additionally produce distortion.

An open switch is also not an ideal infinite impedance. For example, a stipulated $10\mathrm{nA}$ analog switch leakage current into $100\mathrm{pF}$ changes the node potential at $I/C=100V/s$, or $0.10\mathrm{V}$ in a millisecond if that model remains valid. A high-impedance measurement can be sensitive to this small current.

On a bench, compare the transmitted level and the open-state drift with the same source, load and oscilloscope conditions. Analog switch charge injection concerns the control transition itself, while settling time concerns how long the complete circuit needs to approach its final value. Those effects are separate from the static conducting-state error.

Analog switch charge injection is charge transferred to a signal node when the switch control changes. Capacitive coupling from the internal control transition can cause an output step even with a constant analog input. The primary tutorial models coupling through gate-drain capacitance and shows the resulting step separately from retained-charge transients.^[ref]

For a node modeled by total capacitance $C_L$, define $Q_{\mathrm{inj}}$ as the net charge deposited there. Charge balance givesIn an original example, $Q_{\mathrm{inj}}=0.50\mathrm{pC}$ on $C_L=50\mathrm{pF}$ produces a $10\mathrm{mV}$ step. Doubling the capacitance would halve that step if the deposited charge were unchanged. In an actual circuit the charge distribution can also depend on the node impedances and signal level, so that last assumption needs testing.

A useful measurement holds the analog input constant, toggles the control and records the signal node at a specified delay after the transition. Varying load capacitance helps distinguish an approximately fixed charge from other transient effects. Probe capacitance belongs in the node model.

The sign is determined by the circuit and switching direction. A charge step is not the same as a finite switch-on delay or a residual from incomplete discharge. When the switch opens an integrating feedback path, its consequence can be a reset charge-injection pedestal; a longer preceding reset need not remove charge deposited afterward.

Analog switch leakage current is unwanted electric current at an analog switch's signal terminals under stated terminal potentials, switch state and temperature. It can produce a steady offset in a resistive load or accumulate electric charge on an isolated capacitor. The manufacturer's equivalent circuits distinguish on-state and off-state leakage paths; their effects depend on the external circuit.^[ref]

For an original chosen model, let a constant $20\mathrm{pA}$ enter a node with a $50\mathrm{M\Omega }$ resistor to a reference. The steady electric potential difference error is $IR=1.0\mathrm{mV}$. Replacing that load by an initially isolated $200\mathrm{pF}$ capacitor instead givesA $100\mu \mathrm{V}$ drift allowance is exhausted in $1.0\mathrm{ms}$. This leakage-limited hold time assumes constant leakage and capacitance; it ceases to apply if the changing node potential substantially changes the leakage. With both the resistor and capacitor present, $Cdv/dt=I_{\mathrm{leak}}-v/R$ approaches the steady error exponentially.

To measure the effect, hold the switch control fixed, disconnect the intended signal current and record the stored-node slope with known total capacitance. Repeat for relevant terminal potentials and temperatures. Readout input current and board leakage must be included in the measurement model. A one-time step at a control transition instead suggests analog switch charge injection; a sustained slope after that step is a different error mechanism.

Analog switch on-resistance is the conducting path's effective electrical resistance at a specified signal level, supply and temperature. In a locally resistive model, $R_{\mathrm{on}}=\Delta v/i$. It is neither an ideal short circuit nor necessarily constant as the signal moves. Complementary switch devices reduce signal-dependent resistance variation, as the manufacturer's circuit and curves illustrate.^[ref]

An original example drives a $1.0\mathrm{k\Omega }$ load from an ideal source through $R_{\mathrm{on}}=30\Omega$. The voltage divider givesIf the analog switch on-resistance rises to $50\Omega$ elsewhere in the signal range, the ratio becomes $0.95238$, about $1.90\%$ below its first value. One gain correction cannot make both ratios exact. Switch on-resistance flatness therefore matters separately from the minimum resistance; variation with the signal can create nonlinearity.

The same resistance affects dynamics. A stipulated constant $50\Omega$ discharging $2.0\mathrm{nF}$ has RC circuit time constant $0.10\mu \mathrm{s}$ and requires $\tau \log 100\approx 0.461\mu \mathrm{s}$ to reduce an initial residual to one percent. This is a chosen single-pole model; amplifier dynamics can extend the actual integrator reset settling time.

On a bench, measure the terminal drop at known electric current while sweeping the signal level within the permitted range. Separate a nearly constant series loss from its signal-dependent variation. The source resistance and load belong in that measurement; the switch's control propagation delay is not its conducting-path resistance.

An integrator reset establishes the charge on an integrating amplifier's feedback capacitor before the next measurement. Without it, the next output includes the previous initial condition, and repeated input pulses or input offset voltage can eventually cause amplifier clipping. Resetting makes consecutive measurement intervals comparable; it does not reconstruct a pulse already lost to amplifier clipping.

Consider an inverting integrating amplifier with the input held at zero during reset. Place an analog switch across its feedback capacitor $C$. In the approximation of a stable ideal operational amplifier maintaining a virtual ground, a closed switch with constant on-state electrical resistance $R_{\mathrm{on}}$ gives the RC circuit relationThis exponential decay gives an integrator reset settling time for residual magnitude at most $\epsilon$:For stipulated values $C=10\mathrm{nF}$, $R_{\mathrm{on}}=10\mathrm{k\Omega }$ and $|V_{\mathrm{old}}|=0.50\mathrm{V}$, the reset time constant is $100\mu \mathrm{s}$. Reaching a residual of $1\mathrm{mV}$ requires about $621\mu \mathrm{s}$ in this model. Actual amplifier drive, stability and recovery from overload can change the response. A switch's control delay also differs from the full circuit's settling time.^[ref]

Opening the reset switch can itself disturb the initial condition. Analog switch charge injection transfers a small charge to the connected capacitor, producing a reset charge-injection pedestal of magnitudeFor a stipulated $10\mathrm{pC}$ deposited on $10\mathrm{nF}$, this step is $1\mathrm{mV}$. Its sign depends on the circuit and charge direction. A longer reset suppresses the preceding exponential residual but need not suppress the new step created when the switch opens. Analog Devices illustrates this capacitive coupling mechanism and the resulting output step separately from retained-charge settling.^[ref]

A practical experiment repeats zero-input measurements with several reset durations and reads the output at the same delay after switch opening. A decreasing residual indicates incomplete discharge; a persistent offset can instead include reset charge-injection pedestal, input offset voltage and subsequent drift. Repeated readings help separate the reproducible offset from noise. The ACF2101 provides a concrete historical implementation: separate hold and reset controls disconnect the input and discharge the integration capacitor, and its datasheet shows the sequence of hold, integration and reset states.^[ref]

The reset interval also creates integrator reset dead time: charge arriving while the circuit is being reset may not contribute to the next measured integral. Pulse timing relative to the reset therefore matters. A perfectly repeatable baseline alone does not establish that every input pulse was captured.

The integrator reset settling time is the time required to reach a stated error band under the reset/readout sequence. It is not merely the switch's control propagation delay. The primary switch tutorial distinguishes switching time from complete-circuit settling.^[ref]

The integrator reset article derives an ideal residual $V_0{e}^{-T/\tau }$, with $\tau =R_{\mathrm{on}}C$. A focused extension includes an opening pedestal whose magnitude is at most $p$. A conservative final-error bound isTo guarantee $|e|\le \epsilon$ from this bound, require $\epsilon >p$ andwhen the logarithm is positive. This reset error budget with a persistent pedestal assigns separate parts of the tolerance to the residual and the opening event.

For stipulated $|V_0|=0.40\mathrm{V}$, $\tau =20\mu \mathrm{s}$, $p=2\mathrm{mV}$ and $\epsilon =3\mathrm{mV}$, the required duration is about $119.8\mu \mathrm{s}$. A tolerance of $1\mathrm{mV}$ cannot be guaranteed by waiting longer under the same pedestal bound. Accidental cancellation of opposite-sign errors is not a worst-case guarantee.

Measure the output against a stated band at a reproducible delay after opening. Ringing, amplifier drive limits and prior overload can invalidate a single-exponential model; the device datasheet treats output-overload recovery separately.^[ref] The resulting acquisition exclusion is part of integrator reset dead time.

The leakage-limited hold time is the duration for which a stored electric potential difference remains within a stated drift allowance when unwanted electric current changes the stored electric charge. For a constant net leakage $I_{\mathrm{leak}}$ into a fixed capacitance $C$,An allowed drift $\epsilon >0$ therefore gives $T_{\max }=C\epsilon /|I_{\mathrm{leak}}|$. This is a limit from a specified error mechanism, not the complete accuracy or usable duration of an instrument. The ACF2101 datasheet identifies amplifier bias, capacitor leakage and switch leakage as separate contributions to droop.^[ref]

For an original example, a4.7nanofarad capacitor,50picoamperes of net leakage and a0.20millivolt drift allowance giveIf the readout adds a further30picoamperes in the same direction, the correct total is80picoamperes and the duration falls to11.75milliseconds. The relevant electric current is the sum of all paths at the stored node, not necessarily the isolated analog switch leakage current specification.

For time-dependent leakage, the exact charge balance isA verified bound $|I_{\mathrm{net}}(t)|\le I_{\max }$ guarantees $|\Delta v(T)|\le I_{\max }T/C$. Oppositely signed contributions can cancel at one operating point without providing that bound elsewhere. Temperature, terminal potentials and board leakage must match the intended operating conditions.^[ref]

A bench check records the held node at several delays after the switching transient, using a known total capacitance and a readout whose input current is included in the model. The slope estimates net leakage. A step created at the transition is analog switch charge injection, not steady droop. If the initial step already uses part of a total error allowance, only the remaining allowance is available for calculating the leakage-limited hold time.

Switch on-resistance flatness describes how little an analog switch on-resistance changes across a stated analog signal range, at specified supply and temperature. A common measure is the peak-to-peak differenceThe signal interval $\mathcal{V}$ is part of the definition. A small minimum resistance does not establish good switch on-resistance flatness. Analog Devices illustrates how complementary transistor paths flatten the resistance curve and explains the distinction between fixed attenuation and signal-dependent distortion.^[ref]

For an original quasistatic model, an ideal source drives a load $R_L$ through a switch withHere the stipulated resistance law uses the source signal $v$; it is not a transistor model or a device specification. For $|\beta v^2|\ll R_L+r_0$, expansion givesWith $v=A\sin \omega t$, the identity ${\sin }^3\theta =(3\sin \theta -\sin 3\theta )/4$ yieldsA constant gain correction cannot remove the generated third harmonic.

Taking $R_L=1000\Omega$, $r_0=10\Omega$, $\beta =2\Omega /{\mathrm{V}}^2$ and $A=1\mathrm{V}$ gives a resistance range10–12ohms and an approximate third-harmonic amplitude0.490millivolts. Its ratio to the fundamental is about0.050percent. This selected low-frequency calculation isolates a static nonlinearity; it omits switch capacitances and amplifier dynamics.

A practical test holds the switch on, applies a small known electric current, and sweeps the terminal signal level while measuring the conducting-path drop. Measuring several temperatures and supply conditions separates flatness over signal from changes between operating conditions. A second test with a sinusoidal source and Fourier analysis checks whether the complete circuit produces harmonics; source and readout distortion must be measured independently.