Locate an isolated nanowire first, then align source, drain, dielectric and top-gate patterns to it. A suitable research-device sequence is the following; the semiconductor is unspecified, so contact-barrier and surface-cleaning details cannot be assumed universally ohmic.
Prepare a clean electrically insulating substrate, with alignment marks. Disperse a sparse population of nanowires from the suspension, remove the carrier solvent compatibly, and locate a suitable isolated wire by microscopy. Record its position relative to the marks.
Use aligned electron beam lithography and a suitable lift-off process to open contact regions near the two ends while leaving a central channel. Clean the exposed contact regions without destroying the wire, evaporate gold and lift off. The contacts overlap the ends but do not bridge the central channel; test their electrical behavior before assuming an ohmic response.
In a second aligned pattern, define a central dielectric patch that extends beyond the proposed gate edges. Evaporate the specified silicon monoxide and lift off using a profile that permits film separation. Verify coverage over the wire and absence of pinholes: directional deposition onto curved nanoscale geometry is not automatically conformal.
Define and evaporate a gold top gate over that insulated central patch, with its lead kept electrically separated from the source, drain and wire. Lift off and test gate leakage before extracting transistor characteristics. The dielectric must remain continuous under the gate and overlap its edges; the illustrated central gate is not a third direct metal contact to the semiconductor. Gold and silicon monoxide are used as stipulated, without silently replacing SiO by a different oxide.
Articles by others on the same topic
There are currently no matching articles.