Use the phasor convention . The complex impedance is in sinusoidal steady state. From , , and ,
For this convention an ideal inductor has voltage leading current by , while an ideal capacitor has current leading voltage by .
The source diagram has in series with two parallel branches: above and below. With , their complex impedances are and . Their parallel combination is
Thus
The input electric current is in phase with even though the two branch currents separately have nonzero, opposite phase shifts.
Put and , with . The source current is and the parallel-network voltage is . Hence
The voltage from X to each branch midpoint is its resistor drop, so
Since ,
Equal amplitude does not mean equal phase.
Relative to the real positive source phasor ,
Thus lags . Reversing the voltage ordering to would add .

Articles by others on the same topic (0)

There are currently no matching articles.