 Capacitive bridging complex-error bandwidth

The capacitive bridging complex-error bandwidth is the largest frequency over which a receiving port preserves the source phasor within a specified complex relative gain error. The criterion includes phase shift as well as amplitude. A large DC input impedance alone cannot establish this bandwidth when input capacitance matters. The manufacturer's input models explicitly include resistive and capacitive paths.^[ref]

For the scalar impedance bridging with capacitive input model, assume a positive real source electrical resistance $R_s$, receiver resistance $R_{\mathrm{in}}>0$, and input capacitance $C_{\mathrm{in}}>0$ in parallel. Let $V_s$ be the unloaded source phasor. A voltage divider givesFor tolerance $0<\eta <1$, the complex relative gain error isIts square is strictly increasing in $x^2$, since its derivative is $(1+2g)/[(1+g{)}^2+x^2{]}^2>0$. Thus satisfying $E(f)\le \eta$ defines a continuous frequency interval starting at DC, whenever it is feasible. Rearranging givesThe DC error floor is ${\eta }_0=g/(1+g)$. If $\eta <{\eta }_0$, no frequency meets the tolerance; if $\eta ={\eta }_0$, only DC does. The boxed positive bandwidth applies when $\eta >{\eta }_0$.

For an original near-limit example, choose $R_s=10\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$. Then $g=0.01$ and the DC error is about 0.9901 percent. A 1 percent full-complex tolerance leaves onlyAn amplitude-only 1 percent criterion, $|H|\ge 0.99$, instead allows about $2273.47\mathrm{Hz}$. The half-power (approximately $-3\mathrm{dB}$) signal bandwidth, relative to DC, is $(1+g)/(2\pi R_s{C}_{\mathrm{in}})\approx 160.75\mathrm{kHz}$. These are three distinct specifications of this same ideal model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor follows by factoring the numerator:For fixed $g>0$ and $\eta \downarrow {\eta }_0$,This asymptotic equivalence explains the sharp loss of usable bandwidth when the resistive divider has already consumed nearly all the error allowance. Increasing $R_{\mathrm{in}}$ or reducing $R_s$ changes that floor; reducing only $C_{\mathrm{in}}$ rescales a feasible bandwidth but cannot remove infeasibility at DC.

The criterion also controls a complete waveform. Suppose a source waveform $v_s$ is both a square-integrable function and a bandlimited function, with spectrum supported where $|H-1|\le \eta$. For the corresponding zero-state response $v_L$, the Fourier transform of $v_L-v_s$ is $(H-1){\hat{v}}_s$. The Plancherel theorem, or the norm bound for a Fourier multiplier on L2, givesHere the Fourier transform uses the frequency-in-hertz convention, so the displayed Plancherel theorem has no extra normalization factor. This bound includes waveform changes caused by phase. It applies to the zero-state response of the stated frequency response. Any additional homogeneous solution from initially stored energy contributes its own error.

A bench check therefore needs both amplitude ratio and phase shift, with probe and cable capacitance included in the port model. Magnitude-only observations determine $|H|$ without determining $|1-H|$. The formula describes this chosen passive input network; additional amplifier dynamics require their own transfer function.