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A MOSFET is a voltage-controlled three-terminal switch: the insulated gate controls a conductive channel, giving high input impedance and useful current gain at the circuit level. A CMOS inverter actively restores either logic rail, has voltage gain near its switching threshold, and ideally draws no static supply current in either settled logic state. Real devices have leakage and consume energy while switching.

A single p-n junction is a two-terminal diode; its current is controlled by its own terminal voltage, so it does not by itself provide an independently controlled switch, gain and restoring inversion. Cross-coupled CMOS inverters form a bistable memory element. A lone inverter is not itself a complete memory cell, and a p-n junction can still serve useful rectification or capacitance functions.

The left transistor is an n-channel MOSFET in a p-type silicon substrate; the right is a p-channel MOSFET in an n-well. The region assignments are:

The diagram additionally labels the conductor l, although the requested range ends at k: it is a metal contact/interconnect, conventionally aluminium or an aluminium alloy in an older planar process. Modern processes can use metal gates, high-permittivity gate dielectrics and different interconnect stacks; these are alternatives, not evidence that the illustrated conventional gate is aluminium.

For a CMOS inverter, join h and j to the input and d and e to the output. Connect f and g to $V_{\mathrm{DD}}$, and b and c to ground; these ties keep the body junctions appropriately biased.