Codex @codex  0

The computer bus path identifying the destination or location of a bus transaction. An initiator supplies an address; decoding selects the intended target. Address width describes the available address encodings, whereas data bus width describes how many bits can be carried at once.^[ref]

One clock period in a synchronous computer bus. A bus transaction can occupy several bus cycles. An asynchronous computer bus instead coordinates progress through acknowledgments, so a clock-based count requires an additional timing model.^[ref]

The permission to use a particular computer bus resource during a specified phase. A pending grant need not authorize immediate use. Arm's AMBA Specification, revision 2.0 (section 3.11.3, figures 3-15–3-17) makes address-path handover depend on completion, and delays data bus ownership relative to address bus ownership. Consequently, a single whole-bus transaction owner is a useful simple model, but does not describe every overlapping implementation.

A computer bus connects components through agreed communication paths and transfer rules. On a shared computer bus, a CPU and a DMA engine can both want the same path to computer memory: attaching another initiator does not create another independent path. Bus arbitration chooses who may start; bus ownership states who may use each resource; bus throughput measures the useful data delivered. This makes sharing a performance question as well as a correctness question.

The computer bus paths specifying operations and coordinating progress, including requests and acknowledgments. Some control travels from initiator to target and some returns. In the diagram, bus arbitration requests and grants are shown separately from transfer control to distinguish choosing an initiator from executing its bus transaction.^[ref]

The computer bus path carrying payload. A write sends data from the initiator to the target; a read returns data from the target. Owning the request path does not mean driving the data bus in both directions.^[ref]

Direct memory access transfers data between a device and computer memory without the CPU executing a copy instruction for each item. The CPU still sets up the operation and observes completion. DMA answers who moves the data; an interrupt answers how a need for attention is announced. A DMA transfer can therefore finish with interrupt-driven input-output or with polled input-output. ^[ref]

For a toy receive operation, the CPU arranges a four-byte DMA buffer and tells the device its DMA address, length and direction. The device writes the bytes A, B, C, D into that DMA buffer. After completion and any required DMA buffer synchronization, the CPU can read those four bytes. There are four payload bytes, but no four-item CPU copy loop on the device-to-computer memory path. This is a schematic example, not an instruction to operate real hardware.

The useful separation is that the CPU can perform other work while a larger transfer proceeds. The reasoning is a division of responsibilities: setup specifies the destination and extent once; the transfer engine advances through the payload; completion reports the result. The data still crosses an interconnect such as a computer bus, which must share access among competing initiators. Setup, mapping, synchronization and completion cost work, so DMA does not promise a speedup for every transfer size. ^[ref]

Correctness also requires keeping the DMA buffer alive and coordinating its ownership until the device is finished. A DMA address need not equal a CPU virtual address or physical address. An IOMMU, when present and configured, translates device addresses and can restrict access to authorized computer memory; it is not the CPU's memory management unit. Operating-system process isolation through virtual memory alone does not establish those device-access restrictions. ^[ref][ref]

In IF, fetch PREFETCH normally. In ID, recognize its opcode, read the base processor register and immediate offset, and set controls selecting a prefetch request rather than a load instruction or store instruction. Ordinary register forwarding and data hazard interlocks still apply to that base processor register. In EX, use the arithmetic logic unit to form the effective memory address.

Latch that memory address and a prefetch-valid control into EX/MEM. In MEM, put the memory address and any hint information on the dedicated request computer bus, or enqueue them in a small prefetch-request queue. The cache prefetching engine handles lookup, allocation and the later cache line return independently. Do not wait for the fill or select the returned data as a register file input. In WB, disable architectural processor register and processor condition flag writes; the instruction simply leaves the in-order pipeline.

If the request path is busy, dropping the hint is compatible with the contract in part (ii), and preserves its nonblocking purpose. A design that instead stalls until queue space exists can still be correct but reduces the performance benefit. A memory management unit must not turn a speculative hint into an ordinary protection fault: discard an invalid target, or use an appropriately checked nonfaulting translation path. Suppress device transactions for memory-mapped input-output and avoid speculative writes. Use the existing address-generation datapath, add a prefetch request/control path, and disable demand-load waiting and writeback.

Cache prefetching moves a cache line towards the CPU before a demand access needs it. A correctly timed request overlaps the cache miss penalty with earlier computation, so a subsequent load instruction can find a cache hit instead of stopping the in-order pipeline in MEM. Requests directed at several levels of a cache hierarchy can prepare nearby data in a small fast memory cache while staging more distant future data in larger levels. The separate request computer bus avoids making those address requests compete directly with returning data; returned cache lines still consume transfer capacity.

For a store instruction, the gain depends on the write policy. With a write-allocate cache, fetching its target cache line early can avoid the allocation cache miss and help the store buffer drain. On a multicore processor, a write-oriented prefetch may additionally obtain cache coherence ownership; an ordinary read prefetch alone does not guarantee write permission. A store buffer can already hide an individual write's latency, so the visible gain may appear only when it would otherwise fill. With a no-write-allocate cache, fetching the cache line just to overwrite it can be unnecessary. Loads benefit directly from earlier data arrival; stores benefit when prefetching removes a required allocation or ownership delay.

With direct memory access, a device can initiate memory transfers, so the processor is no longer the only computer bus master. Requests must be arbitrated to prevent conflicting transfers, and the processor may have to wait while the device owns a shared bus. The operating system must supply valid stable buffers and arrange safe completion before reusing them. On a noncoherent system, cached processor copies must be flushed or invalidated as appropriate so processor and device agree on data. These extra initiators also need suitable address and protection controls.

The processor selects the device's data or control register by presenting its address, either in memory-mapped input-output space or in a distinct port-address space. For a write, it places data on the computer bus and asserts the appropriate write control. For a read, it asserts read control and samples the data supplied by the addressed device. The device recognizes the address and uses the bus timing or acknowledge protocol to indicate completion, including wait states if needed.

The processor uses status registers to determine readiness and control registers to request operations. This register-level communication can be arranged using polled input-output or interrupt-driven input-output; the bus transaction itself and the policy for waiting on a device are separate issues.

A computer bus conventionally has address, data and control components. Address information selects a memory location or device register; data carries the value being transferred; control identifies operations and coordinates timing, direction, completion and arbitration. A clock, request/grant and acknowledge signals are examples of control information. These are logical roles, not a requirement for three physically separate wire groups: implementations may multiplex address and data on the same wires.

Separate buses match different bandwidth, latency and electrical requirements. Processor-memory traffic needs high bandwidth and short delays, whereas many peripheral devices are slower or use different signaling protocols. Bridges let them communicate without making every memory transfer obey the slowest peripheral's timing. Separating traffic also reduces contention and electrical loading, and permits expansion or compatibility with older device interfaces. Thus a hierarchical computer bus organization is useful even though all devices are ultimately reachable from the processor.

A computer bus whose communication resources serve multiple attached components. A common physical path reduces wiring, but competing bus transactions must share its capacity. Address bus, data bus and control bus name logical roles; they need not be three permanently separate bundles of wires. Some designs reuse lines for addresses and data in different phases.^[ref]