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The computer bus path identifying the destination or location of a bus transaction. An initiator supplies an address; decoding selects the intended target. Address width describes the available address encodings, whereas data bus width describes how many bits can be carried at once.^[ref]

One clock period in a synchronous computer bus. A bus transaction can occupy several bus cycles. An asynchronous computer bus instead coordinates progress through acknowledgments, so a clock-based count requires an additional timing model.^[ref]

The permission to use a particular computer bus resource during a specified phase. A pending grant need not authorize immediate use. Arm's AMBA Specification, revision 2.0 (section 3.11.3, figures 3-15–3-17) makes address-path handover depend on completion, and delays data bus ownership relative to address bus ownership. Consequently, a single whole-bus transaction owner is a useful simple model, but does not describe every overlapping implementation.

A computer bus connects components through agreed communication paths and transfer rules. On a shared computer bus, a CPU and a DMA engine can both want the same path to computer memory: attaching another initiator does not create another independent path. Bus arbitration chooses who may start; bus ownership states who may use each resource; bus throughput measures the useful data delivered. This makes sharing a performance question as well as a correctness question.

The computer bus paths specifying operations and coordinating progress, including requests and acknowledgments. Some control travels from initiator to target and some returns. In the diagram, bus arbitration requests and grants are shown separately from transfer control to distinguish choosing an initiator from executing its bus transaction.^[ref]

The computer bus path carrying payload. A write sends data from the initiator to the target; a read returns data from the target. Owning the request path does not mean driving the data bus in both directions.^[ref]

Direct memory access transfers data between a device and computer memory without the CPU executing a copy instruction for each item. The CPU still sets up the operation and observes completion. DMA answers who moves the data; an interrupt answers how a need for attention is announced. A DMA transfer can therefore finish with interrupt-driven input-output or with polled input-output. ^[ref]

For a toy receive operation, the CPU arranges a four-byte DMA buffer and tells the device its DMA address, length and direction. The device writes the bytes A, B, C, D into that DMA buffer. After completion and any required DMA buffer synchronization, the CPU can read those four bytes. There are four payload bytes, but no four-item CPU copy loop on the device-to-computer memory path. This is a schematic example, not an instruction to operate real hardware.

The useful separation is that the CPU can perform other work while a larger transfer proceeds. The reasoning is a division of responsibilities: setup specifies the destination and extent once; the transfer engine advances through the payload; completion reports the result. The data still crosses an interconnect such as a computer bus, which must share access among competing initiators. Setup, mapping, synchronization and completion cost work, so DMA does not promise a speedup for every transfer size. ^[ref]

Correctness also requires keeping the DMA buffer alive and coordinating its ownership until the device is finished. A DMA address need not equal a CPU virtual address or physical address. An IOMMU, when present and configured, translates device addresses and can restrict access to authorized computer memory; it is not the CPU's memory management unit. Operating-system process isolation through virtual memory alone does not establish those device-access restrictions. ^[ref][ref]

A computer bus whose communication resources serve multiple attached components. A common physical path reduces wiring, but competing bus transactions must share its capacity. Address bus, data bus and control bus name logical roles; they need not be three permanently separate bundles of wires. Some designs reuse lines for addresses and data in different phases.^[ref]