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Analog switch on-resistance is the conducting path's effective electrical resistance at a specified signal level, supply and temperature. In a locally resistive model, $R_{\mathrm{on}}=\Delta v/i$. It is neither an ideal short circuit nor necessarily constant as the signal moves. Complementary switch devices reduce signal-dependent resistance variation, as the manufacturer's circuit and curves illustrate.^[ref]

An original example drives a $1.0\mathrm{k\Omega }$ load from an ideal source through $R_{\mathrm{on}}=30\Omega$. The voltage divider givesIf the analog switch on-resistance rises to $50\Omega$ elsewhere in the signal range, the ratio becomes $0.95238$, about $1.90\%$ below its first value. One gain correction cannot make both ratios exact. Switch on-resistance flatness therefore matters separately from the minimum resistance; variation with the signal can create nonlinearity.

The same resistance affects dynamics. A stipulated constant $50\Omega$ discharging $2.0\mathrm{nF}$ has RC circuit time constant $0.10\mu \mathrm{s}$ and requires $\tau \log 100\approx 0.461\mu \mathrm{s}$ to reduce an initial residual to one percent. This is a chosen single-pole model; amplifier dynamics can extend the actual integrator reset settling time.

On a bench, measure the terminal drop at known electric current while sweeping the signal level within the permitted range. Separate a nearly constant series loss from its signal-dependent variation. The source resistance and load belong in that measurement; the switch's control propagation delay is not its conducting-path resistance.

An integrator reset establishes the charge on an integrating amplifier's feedback capacitor before the next measurement. Without it, the next output includes the previous initial condition, and repeated input pulses or input offset voltage can eventually cause amplifier clipping. Resetting makes consecutive measurement intervals comparable; it does not reconstruct a pulse already lost to amplifier clipping.

Consider an inverting integrating amplifier with the input held at zero during reset. Place an analog switch across its feedback capacitor $C$. In the approximation of a stable ideal operational amplifier maintaining a virtual ground, a closed switch with constant on-state electrical resistance $R_{\mathrm{on}}$ gives the RC circuit relationThis exponential decay gives an integrator reset settling time for residual magnitude at most $\epsilon$:For stipulated values $C=10\mathrm{nF}$, $R_{\mathrm{on}}=10\mathrm{k\Omega }$ and $|V_{\mathrm{old}}|=0.50\mathrm{V}$, the reset time constant is $100\mu \mathrm{s}$. Reaching a residual of $1\mathrm{mV}$ requires about $621\mu \mathrm{s}$ in this model. Actual amplifier drive, stability and recovery from overload can change the response. A switch's control delay also differs from the full circuit's settling time.^[ref]

Opening the reset switch can itself disturb the initial condition. Analog switch charge injection transfers a small charge to the connected capacitor, producing a reset charge-injection pedestal of magnitudeFor a stipulated $10\mathrm{pC}$ deposited on $10\mathrm{nF}$, this step is $1\mathrm{mV}$. Its sign depends on the circuit and charge direction. A longer reset suppresses the preceding exponential residual but need not suppress the new step created when the switch opens. Analog Devices illustrates this capacitive coupling mechanism and the resulting output step separately from retained-charge settling.^[ref]

A practical experiment repeats zero-input measurements with several reset durations and reads the output at the same delay after switch opening. A decreasing residual indicates incomplete discharge; a persistent offset can instead include reset charge-injection pedestal, input offset voltage and subsequent drift. Repeated readings help separate the reproducible offset from noise. The ACF2101 provides a concrete historical implementation: separate hold and reset controls disconnect the input and discharge the integration capacitor, and its datasheet shows the sequence of hold, integration and reset states.^[ref]

The reset interval also creates integrator reset dead time: charge arriving while the circuit is being reset may not contribute to the next measured integral. Pulse timing relative to the reset therefore matters. A perfectly repeatable baseline alone does not establish that every input pulse was captured.

Integrator reset dead time is the interval during which incoming charge is excluded from the reported measurement because the integrator is resetting or not yet ready for acquisition. A switched-integrator implementation has distinct integration, hold and reset states; the historical datasheet shows those states and their timing.^[ref]

For an original periodic schedule, acquire during the first $80\mu \mathrm{s}$ of every $100\mu \mathrm{s}$ cycle, reset for the next $10\mu \mathrm{s}$ and exclude the final $10\mu \mathrm{s}$ for settling. The duty cycle is $80\%$. If short-pulse arrival phases are independent and uniform over that cycle, the expected captured fraction is $0.80$.

That fraction does not apply to every pulse train. Pulses spaced by $100\mu \mathrm{s}$ and arriving at phase $85\mu \mathrm{s}$ are all missed in the ideal schedule. The same train at phase $20\mu \mathrm{s}$ is entirely captured. The clock synchronization matters as much as the fraction of time spent acquiring.

A bench check compares accepted events with an independent pulse monitor while changing their phase relative to the reset command. State whether the excluded interval includes the switch delay, discharge interval, post-opening transient and readout recovery. A stable zero-input baseline alone cannot demonstrate that every pulse was accepted. The integrator reset settling time and a reset charge-injection pedestal concern readiness and initial conditions, while dead time concerns which signal arrivals contribute at all.

A reset error budget with a persistent pedestal assigns separate tolerance to a decaying pre-reset residual and an offset created when the reset switch opens. Increasing the preceding discharge time can reduce the former without reducing the latter. The integrator reset settling time article derives the basic worst-case bound and its logarithmic reset-duration requirement.

A focused extension includes leakage during a fixed post-opening readout delay $d$. Let the pre-reset residual magnitude be at most $R$, its decay time constant be $\tau$, the opening reset charge-injection pedestal magnitude be at most $p$, and subsequent electric current magnitude be at most $I_{\max }$ on fixed capacitance $C$. The triangle inequality givesThis separates a duration-controlled term from an error floor $F=p+I_{\max }d/C$. For $R>0$ and a required guarantee $|e|\le \epsilon$, finite reset time is possible from this bound only when $\epsilon >F$, and

For an original chosen circuit, take $R=0.10\mathrm{V}$, $\tau =5\mu \mathrm{s}$, $p=0.50\mathrm{mV}$, $C=100\mathrm{pF}$, $I_{\max }=1.0\mathrm{nA}$ and $d=20\mu \mathrm{s}$. Leakage consumes $0.20\mathrm{mV}$. A $1.0\mathrm{mV}$ total tolerance leaves $0.30\mathrm{mV}$ for the old residual, requiring about $29.0\mu \mathrm{s}$ of reset. A $0.60\mathrm{mV}$ tolerance requires changing the stipulated pedestal or readout conditions; reset duration alone cannot guarantee it.

These are worst-case bounds, not root-sum-square standard uncertainties. Test the discharge by varying $T$, the opening step with zero-input records, and the subsequent drift by varying $d$. Real charge transfer depends on switching sequence, and prior overload can require separate recovery.^[ref] Accidental cancellation of signed errors is not a reproducible worst-case margin.