Optical component Updated 2025-07-16
Variety Jones Updated 2025-07-16
2023 Silk Road's Second-in-Command Gets 20 Years in Prison www.wired.com/story/silk-road-variety-jones-sentencing/
2016 "Exclusive: Our Thai prison interview with the alleged top advisor to Silk Road" arstechnica.com/tech-policy/2016/09/exclusive-our-thai-prison-interview-with-an-alleged-top-advisor-to-silk-road/
2015 The Variety Show On the trail of the man believed to be Variety Jones, one of the architects of the defunct drug marketplace Silk Road. www.vice.com/en/article/wnx5qn/the-variety-show
www.justice.gov/usao-sdny/file/797251/download some kind of case file of his trial.
Bibliography:
The curious thing about VJ is that he actually has some culture and says cool things, e.g.:
Vector (mathematics) Updated 2025-07-16
City in the United Kingdom Updated 2025-07-16
Holonomic function Updated 2025-07-16
Regular expression Updated 2025-07-16
The truth will set you free Updated 2025-07-16
Zermelo-Fraenkel set theory Updated 2025-10-14
One of the first formal proof systems. This is actually understandable!
This is Ciro Santilli-2020 definition of the foundation of mathematics (and the only one he had any patience to study at all).
TODO what are its limitations? Why were other systems created?
Media rationale of Ciro Santilli's website Updated 2025-07-16
Verilator Updated 2025-07-16
One very good thing about this is that it makes it easy to create test cases directly in C++. You just supply inputs and clock the simulation directly in a C++ loop, then read outputs and assert them with
assert(). And you can inspect variables by printing them or with GDB. This is infinitely more convenient than doing these IO-type tasks in Verilog itself.Some simulation examples under verilog.
First install Verilator. On Ubuntu:Tested on Verilator 4.038, Ubuntu 22.04.
sudo apt install verilatorRun all examples, which have assertions in them:
cd verilator
make runFile structure is for example:
- verilog/counter.v: Verilog file
- verilog/counter.cpp: C++ loop which clocks the design and runs tests with assertions on the outputs
- verilog/counter.params: gcc compilation flags for this example
- verilog/counter_tb.v: Verilog version of the C++ test. Not used by Verilator. Verilator can't actually run out
_tbfiles, because they do in Verilog IO things that we do better from C++ in Verilator, so Verilator didn't bother implementing them. This is a good thing.
Example list:
- verilog/negator.v, verilog/negator.cpp: the simplest non-identity combinatorial circuit!
- verilog/counter.v, verilog/counter.cpp: sequential hello world. Synchronous active high reset with active high enable signal. Adapted from: www.asic-world.com/verilog/first1.html
- verilog/subleq.v, verilog/subleq.cpp: subleq one instruction set computer with separated instruction and data RAMs
Yeast artificial chromosome Updated 2025-07-16
Skew-symmetric form Updated 2025-07-16
Human spinal cord Updated 2025-07-16
Supercomputer by owner Updated 2025-07-16
Particle in a box Updated 2025-07-16
Superfluid helium-4 Updated 2025-07-16
Also sometimes called helium II, in contrast to helium I, which is the non-superfluid liquid helium phase.
Hadamard gate Updated 2025-07-16
The Hadamard gate takes or (quantum states with probability 1.0 of measuring either 0 or 1), and produces states that have equal probability of 0 or 1.
Spin half Updated 2025-07-16
Leads to the Dirac equation.
Rydberg atom Updated 2025-07-16
Spin 1 Updated 2025-07-16
Leads to the Proca equation.
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