webpack Updated 2025-07-16
Webpack is like a magic hydra that can eat any type of file and bundle it into a single output: .js, .ts, .ccs, .scss, .jsx, .tsx,
require, import, import css from .js, it doesn't matter at all, it just digests all into the same dump.When it works, you are just left in awe and with a single Js file. When it doesn't, you're fucked and have to debug for several hours.
Demos under: webpack/. To run all of them by default:To easily make changes and reload the .js output live let this run on a terminal:
cd webpack/min
npm install
npm run build
xdg-open index.htmlnpx webpack watchExamples:
- webpack/min: minimal hello world. Doesn't do much, just copies
index.jstodist/index.js. - webpack/require:
requireandimportdemo. Both work from the same file.dist/index.jsnow contains all of:notindex.jsnotindex2.js- Lodash, a common third-party helper library specified in the package.json and installed with npm
- webpack/node: produce Node.js output, as opposed to the default web output. To test it run:Achieved simply with:
npm run build node dist/index.jsas documented at: webpack.js.org/concepts/targets/target: 'node'Fatman in Robin, - webpack/sequelize: attempts at getting Sequelize to work with webpack. It's just not supported by Sequelize:
Website Updated 2025-07-16
What does it mean that photons are force carriers for electromagnetism? Updated 2025-07-16
TODO find/create decent answer.
I think the best answer is something along:
- local symmetries of the Lagrangian imply conserved currents. gives conserved charges.
- OK now. We want a local symmetry. And we also want:Given all of that, the most obvious and direct thing we reach a guess at the quantum electrodynamics Lagrangian is Video "Deriving the qED Lagrangian by Dietterich Labs (2018)"
- Dirac equation: quantum relativistic Newton's laws that specify what forces do to the fields
- electromagnetism: specifies what causes forces based on currents. But not what it does to masses.
A basic non-precise intuition is that a good model of reality is that electrons do not "interact with one another directly via the electromagnetic field".
A better model happens to be the quantum field theory view that the electromagnetic field interacts with the photon field but not directly with itself, and then the photon field interacts with parts of the electromagnetic field further away.
The more precise statement is that the photon field is a gauge field of the electromagnetic force under local U(1) symmetry, which is described by a Lie group. TODO understand.
This idea was first applied in general relativity, where Einstein understood that the "force of gravity" can be understood just in terms of symmetry and curvature of space. This was later applied o quantum electrodynamics and the entire Standard Model.
From Video "Lorenzo Sadun on the "Yang-Mills and Mass Gap" Millennium problem":
- www.youtube.com/watch?v=pCQ9GIqpGBI&t=1663s mentions this idea first came about from Hermann Weyl.
- youtu.be/pCQ9GIqpGBI?t=2827 mentions that in that case the curvature is given by the electromagnetic tensor.
Bibliography:
- www.youtube.com/watch?v=qtf6U3FfDNQ Symmetry and Quantum Electrodynamics (The Standard Model Part 1) by ZAP Physics (2021)
- www.youtube.com/watch?v=OQF7kkWjVWM The Symmetry and Simplicity of the Laws of Nature and the Higgs Boson by Juan Maldacena (2012). Meh, also too basic.
When the École Polytechnique mathematics department didn't let Ciro Santilli do his internship of choice due to grades Updated 2025-07-16
This was one of the only bad experience Ciro had at Polytechnique, besides the inevitable fear of not graduating.
Ciro wanted to do a robotics internship in Germany, linked to his interests in artificial general intelligence, see also: Section "Ciro's 2D reinforcement learning games".
But the head of the applied mathematics department Polytechnique prevented him from going because Ciro didn't have the necessary grades, even though the Germans had already agreed to it: he had a C, but he needed a B. As mentioned at École Polytechnique, most Brazilians had crappy grades due to their Polytechnique-incompatible background.
This was done because in the past students with bad grades had abandoned their internships halfway and given foreigners a bad impression of Polytechnique.
It is impossible to say if the head of department really agreed with this bullshit policy, or if it was something beyond his powers and he hid his true opinion, but it felt like the agreed.
What an extremely limited view!!!
To leave the worse, the worse. To assume that grades mean anything!
And thus Ciro had to choose a last moment internship that he hated, rather than becoming the greatest roboticist that ever lived, and did terribly at it.
At least on the other hand Ciro learnt Python instead of working at the internship, and became the greatest programming tutorial writer that ever lived. Maybe.
Whole cell simulation Updated 2025-07-16
Ciro Santilli started taking some notes at: github.com/cirosantilli/awesome-whole-cell-simulation. but they are going to be all migrated here.
It is interesting to note how one talks about single cell analysis, in contrast to whole cell simulation: experimentally it is hard to analyse a single cell. But theoretically, it is hard to simulate a single cell. This mismatch is perhaps the ultimate frontier of molecular biology.
Why are complex numbers used in the Schrodinger equation? Updated 2025-07-16
This useless video doesn't really explain anything, he just says "it's needed because the equation has an in it".
The real explanation is: they are not needed, they just allow us to write the equation in a shorter form, which is always a win: physics.stackexchange.com/questions/32422/qm-without-complex-numbers/557600#557600
Why can't you collimate incoherent light as well as a laser? Updated 2025-07-16
You could put an LED in a cavity with a thin long hole but then, most rays, which are not aligned with the hole, will just bounce inside forever producing heat.
So you would have a very hot device, and very little efficiency on the light output. This heat might also behave like a black-body radiation source, so you would not have a single frequency.
The beauty of lasers is the laser cavity (two parallel mirrors around the medium) selects parallel motion preferentially, see e.g.: youtu.be/_JOchLyNO_w?t=832 from Video "How Lasers Work by Scientized (2017)"
How to blackout your window without drilling Previous failed attempts Updated 2025-07-16
Thick cardboard paper and Gorilla Tape: the intense Sun heat made the cardboard bend, and even the Gorilla tape could not hold it, leading to light leakage. Even worse, it started to smell a bit, and I got afraid that it could catch fire, so don't do this! Maybe I will try coating with aluminium foil next time, but I'm afraid it might stick to the glass. In any case, even if those setups work, your room may be permanently very dark depending on how far the window opens, which can lead to other problems such as mold. Another downside of this method is that the tape is extremely sticky, and especially difficult to remove if it touches the glass, where you can't use metallic items to scrape it off without scratching the glass. I had to get a solvent and use a lot of elbow grease to get rid of it.
I have tried a few sleeping masks, but none of them were enough on their own. There is always some light leakage around the nose, especially as you turn around in the night. And some of them are too hot. I have tried:
- Sleep Master (archive): www.amazon.co.uk/gp/product/B0015NZ6FK (archive). Also too hot.
- Muji Eye Mask
I also considered getting one of those "Perfect Fit Blinds" www.blindsdirect.co.uk/perfect-fit-roller-blinds (archive) which fit between the glass and the insulation. This looks like it could work. But I didn't go for it in the end because my window has 3 glass panels, so I would have to get three of those blinds separately.
x86 custom instructions Updated 2025-07-16
Intel is known to have created customized chips for very large clients.
This is mentioned e.g. at: www.theregister.com/2021/03/23/google_to_build_server_socs/Those chips are then used only in large scale server deployments of those very large clients. Google is one of them most likely, given their penchant for Google custom hardware.
Intel is known to do custom-ish cuts of Xeons for big customers.
TODO better sources.
x86 Paging Tutorial Updated 2025-07-19
This tutorial explains the very basics of how paging works, with focus on x86, although most high level concepts will also apply to other instruction set architectures, e.g. ARM.
The goals are to:
This tutorial was extracted and expanded from this Stack Overflow answer.
x86 Paging Tutorial 64-bit architectures Updated 2025-07-16
x86_64 uses 48 bits (256 TiB), and legacy mode's PAE already allows 52-bit addresses (4 PiB). 56-bits is a likely future candidate.
But that would mean that the page directory would have
2^18 = 256K entries, which would take too much RAM: close to a single-level paging for 32 bit architectures!x86_64 uses 4 levels in a
9 | 9 | 9 | 9 scheme, so that the upper level only takes up only 2^9 higher level entries.The 48 bits are split equally into two disjoint parts:
----------------- FFFFFFFF FFFFFFFF
Top half
----------------- FFFF8000 00000000
Not addressable
----------------- 00007FFF FFFFFFFF
Bottom half
----------------- 00000000 00000000A 5-level scheme is emerging in 2016: software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf which allows 52-bit addresses with 4k pagetables.
x86 Paging Tutorial Multi-level paging scheme numerical translation example Updated 2025-07-16
Page directory given to process by the OS:
entry index entry address page table address present
----------- ---------------- ------------------ --------
0 CR3 + 0 * 4 0x10000 1
1 CR3 + 1 * 4 0
2 CR3 + 2 * 4 0x80000 1
3 CR3 + 3 * 4 0
...
2^10-1 CR3 + 2^10-1 * 4 0Page tables given to process by the OS at
PT1 = 0x10000000 (0x10000 * 4K):entry index entry address page address present
----------- ---------------- ------------ -------
0 PT1 + 0 * 4 0x00001 1
1 PT1 + 1 * 4 0
2 PT1 + 2 * 4 0x0000D 1
... ...
2^10-1 PT1 + 2^10-1 * 4 0x00005 1Page tables given to process by the OS at where
PT2 = 0x80000000 (0x80000 * 4K):entry index entry address page address present
----------- --------------- ------------ ------------
0 PT2 + 0 * 4 0x0000A 1
1 PT2 + 1 * 4 0x0000C 1
2 PT2 + 2 * 4 0
...
2^10-1 PT2 + 0x3FF * 4 0x00003 1PT1 and PT2: initial position of page table 1 and page table 2 for process 1 on RAM.With that setup, the following translations would happen:
linear 10 10 12 split physical
-------- -------------- ----------
00000001 000 000 001 00001001
00001001 000 001 001 page fault
003FF001 000 3FF 001 00005001
00400000 001 000 000 page fault
00800001 002 000 001 0000A001
00801004 002 001 004 0000C004
00802004 002 002 004 page fault
00B00001 003 000 000 page faultLet's translate the linear address
0x00801004 step by step:- In binary the linear address is:
0 0 8 0 1 0 0 4 0000 0000 1000 0000 0001 0000 0000 0100 - Grouping as
10 | 10 | 12gives:which gives:0000000010 0000000001 000000000100 0x2 0x1 0x4So the hardware looks for entry 2 of the page directory.page directory entry = 0x2 page table entry = 0x1 offset = 0x4 - The page directory table says that the page table is located at
0x80000 * 4K = 0x80000000. This is the first RAM access of the process. - Finally, the paging hardware adds the offset, and the final address is
0x0000C004.
The Intel manual gives a picture of this translation process in the image "Linear-Address Translation to a 4-KByte Page using 32-Bit Paging": Figure 1. "x86 page translation process"
x86 page translation process
. Erdős number Updated 2025-10-27
Discrete logarithm Updated 2025-10-27
An important case is the discrete logarithm of the cyclic group in which the group is a cyclic group.
x86 Paging Tutorial Application Updated 2025-07-16
Paging makes it easier to compile and run two programs or threads at the same time on a single computer.
For example, when you compile two programs, the compiler does not know if they are going to be running at the same time or not.
And thread stacks, that must be contiguous and keep growing down until they overwrite each other, are an even bigger issue!
But if two programs use the same address and run at the same time, this is obviously going to break them!
Paging solves this problem beautifully by adding one degree of indirection:
(logical) ------------> (physical)
pagingWhere:
As far as programs are concerned, they think they can use any address between 0 and 4 GiB (2^32,
FFFFFFFF) on 32-bit systems.The OS then sets up paging so that identical logical addresses will go into different physical addresses and not overwrite each other.
This makes it much simpler to compile programs and run them at the same time.
Paging achieves that goal, and in addition:
- the switch between programs is very fast, because it is implemented by hardware
- the memory of both programs can grow and shrink as needed without too much fragmentation
- one program can never access the memory of another program, even if it wanted to.This is good both for security, and to prevent bugs in one program from crashing other programs.
Or if you like non-funny jokes:
Comparison between the Linux kernel userland memory virtualization and The Matrix
. Source. Is this RAM real?
x86 Paging Tutorial CAM Updated 2025-07-16
Using the TLB makes translation faster, because the initial translation takes one access per TLB level, which means 2 on a simple 32 bit scheme, but 3 or 4 on 64 bit architectures.
The TLB is usually implemented as an expensive type of RAM called content-addressable memory (CAM). CAM implements an associative map on hardware, that is, a structure that given a key (linear address), retrieves a value.
Mappings could also be implemented on RAM addresses, but CAM mappings may required much less entries than a RAM mapping.
linear physical
------ --------
00000 00001
00001 00010
00010 00011
FFFFF 00000 x86 Paging Tutorial Hardware implementation Updated 2025-07-16
Paging is implemented by the CPU hardware itself.
Paging could be implemented in software, but that would be too slow, because every single RAM memory access uses it!
Operating systems must setup and control paging by communicating to the CPU hardware. This is done mostly via:
- the CR3 register, which tells the CPU where the page table is in RAM memory
- writing the correct paging data structures to the RAM pointed to the CR3 register.Using RAM data structures is a common technique when lots of data must be transmitted to the CPU as it would cost too much to have such a large CPU register.The format of the configuration data structures is fixed by the hardware, but it is up to the OS to set up and manage those data structures on RAM correctly, and to tell the hardware where to find them (via
cr3).Then some heavy caching is done to ensure that the RAM access will be fast, in particular using the TLB.Another notable example of RAM data structure used by the CPU is the IDT which sets up interrupt handlers. - CR3 cannot be modified in ring 3. The OS runs in ring 0. See also:
- the page table structures are made invisible to the process using paging itself!
Processes can however make requests to the OS that cause the page tables to be modified, notably:
- stack size changes
brkandmmapcalls, see also: stackoverflow.com/questions/6988487/what-does-brk-system-call-do/31082353#31082353
The kernel then decides if the request will be granted or not in a controlled manner.
x86 Paging Tutorial How the K-ary tree is used in x86 Updated 2025-07-16
Addresses are now split as:
| directory (10 bits) | table (10 bits) | offset (12 bits) |Then:
- The top table is called a "directory of page tables".
cr3now points to the location on RAM of the page directory of the current process instead of page tables.Page directory entries are very similar to page table entries except that they point to the physical addresses of page tables instead of physical addresses of pages.Each directory entry also takes up 4 bytes, just like page entries, so that makes 4 KiB per process minimum.Page directory entries also contain a valid flag: if invalid, the OS does not allocate a page table for that entry, and saves memory.Each process has one and only one page directory associated to it (and pointed to bycr3), so it will contain at least2^10 = 1Kpage directory entries, much better than the minimum 1M entries required on a single-level scheme. - Second level entries are also called page tables like the single level scheme.Each page table has only
2^10 = 1Kpage table entries instead of2^20for the single paging scheme. - the offset is again not used for translation, it only gives the offset within a page
One reason for using 10 bits on the first two levels (and not, say,
12 | 8 | 12 ) is that each Page Table entry is 4 bytes long. Then the 2^10 entries of Page directories and Page Tables will fit nicely into 4Kb pages. This means that it faster and simpler to allocate and deallocate pages for that purpose. x86 Paging Tutorial Linux kernel usage Updated 2025-07-16
The Linux kernel makes extensive usage of the paging features of x86 to allow fast process switches with small data fragmentation.
There are also however some features that the Linux kernel might not use, either because they are only for backwards compatibility, or because the Linux devs didn't feel it was worth it yet.
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