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A control that resets stored state independently of the clock edge. An active-low clear is asserted by a low signal; clocked sampling resumes after the clear is released.

A recurring digital signal whose designated clock edge triggers a state update. A rising clock edge is the transition from the low level to the high level; a falling clock edge is the reverse.

A Boolean circuit whose current output depends only on its current input, with no stored state or feedback dependency. Its delay is bounded by the longest input-to-output path of logic gates. This differs from a synchronous sequential circuit, whose output can depend on state stored at earlier clock edges.

A sampled toggle controller can reject short disturbances by requiring three consecutive high samples to toggle, and then three consecutive low samples before another high run is allowed to toggle. One four-bit synchronous sequential circuit stores output $z$, an armed bit $e$, and input history $p,q$. Initially $(p,q,e,z)=(0,0,1,0)$. SetThe two three-sample run detectors cannot assert simultaneously. A high run toggles once and clears $e$; only a complete low run rearms it. All right-hand sides use the old state, so the toggling event occurs at the third qualifying clock edge.

The controller has twelve distinguishable behaviours: for each $z$, three armed states count trailing highs of lengths $0,1,2$, and three disarmed states count trailing lows of lengths $0,1,2$. The run lengths are distinguished by the number of further matching samples needed before a toggle or rearm. Armed and disarmed states are distinguished by an all-high continuation. Thus at least $\lceil {\log }_{2}12\rceil =4$ state bits are required, and the displayed design attains that bound.

At the active clock edge, $Q^{+}=D$. An asynchronous clear, when provided and asserted, takes precedence over this data-sampling rule.

A flip-flop stores one bit and updates it at a specified clock edge; an asynchronous clear can override that clocked update. Signal polarity is part of the specification, not something inferred from the name alone.

At the active clock edge, the next state is $Q^{+}=J\neg Q\vee \neg KQ$: inputs $00$ hold, $01$ reset, $10$ set, and $11$ toggle. In particular, $K=0$ gives $Q^{+}=J\vee Q$, whereas $J=K=1$ gives $Q^{+}=\neg Q$. The standard function table is illustrated by a positive-edge device in the ^[ref]. Its asynchronous reset is active high; another circuit may specify an active-low clear.

A Moore machine is a finite-state machine whose output depends only on the current state. In a clocked implementation, a state entered at a clock edge determines the following period's output. Specifying an initial state is necessary to define startup behavior.

After asserting and releasing the active-low Start pulse, a valid sequence is $X_0\uparrow$, then $X_1\uparrow$, then $X_2\uparrow$, with each input held high through the relevant sampling interval. The first JK flip-flop has $J=X_0,K=0$ and is clocked by $X_1$, so the rising clock edge of $X_1$ samples $X_0=1$ and sets $Y_0=1$. Once that output has settled, a rising clock edge of $X_2$ clocks the second JK flip-flop with $J=Y_0=1,K=0$, setting $Y_1=1$.

The essential conditions concern sampled levels: $X_0$ must be high at a rising clock edge of $X_1$, and $Y_0$ must then be high at a rising clock edge of $X_2$. Separate edges with adequate setup and hold time avoid an ambiguous simultaneous transition.

The initial input levels do not initialize the stored bits. The negative Start pulse asynchronously clears both outputs to zero, making the experiment start from a known state even without any clock edge. Once Start is released, the circuit can recognize a fresh sequence. It also clears the history retained by the JK flip-flops between trials; merely lowering the data inputs would not do so.

With $K=0$, a JK flip-flop obeys $Q^{+}=J\vee Q$ at its positive clock edge: $J=0$ holds its old state and $J=1$ sets it. Thus each original stage is a sticky record of a previously sampled high input until Start clears it. A D flip-flop instead obeys $Q^{+}=D$, so a later sample of zero can clear the output.

Connect each replacement D input where the corresponding J input was connected, preserving the clocks and asynchronous clear. The first valid sequence after Start still sets both outputs. Afterwards, let $X_0$ fall and apply another rising clock edge to $X_1$. The D version clears $Y_0$; the JK version retains $Y_0=1$. A subsequent rising clock edge of $X_2$ can therefore clear $Y_1$ only in the D version. Neither circuit continuously tracks its data input between clock edges.

Connect the fourth JK flip-flop with $J_3=K_3=1$ and clock it from $Q_2$, retaining the source's positive-edge convention. Read the four-bit state as $Q_3{Q}_2{Q}_1{Q}_0$. Its state-transition diagram is a single cyclewith one input rising clock edge per arrow; the figure displays every state explicitly.

Each stage halves the preceding triggering frequency. $Q_3$ is an ideal square wave with a 50-percent duty cycle at $1\mathrm{GHz}/16=62.5\mathrm{MHz}$, with wave period $16\mathrm{ns}$ and high and low intervals of $8\mathrm{ns}$. Its initial phase depends on the starting state. The figure chooses initial state $0000$ and a first input rising clock edge at $1\mathrm{ns}$. Actual ripple propagation shifts edge times and creates intermediate transient codes; no device delays were supplied, so the waveform describes settled ideal logic.

Use a three-sample run detector. Just before clock edge $t$, let two stored bits $p$ and $q$ hold the input values at edges $t-1$ and $t-2$. Initialise both to zero. With input $a_t$, definePrimes denote the next stored state, with all assignments simultaneous at the clock edge. The output is the logical conjunction of the present input and its two preceding samples. By induction on clock edges, the stated interpretation of $p,q$ is maintained, proving the required behaviour. Two bits of state suffice.

Store two bits: the output $z$, initially zero, and an armed bit $e$, initially one. Define the synchronous sequential circuit byHere $\oplus$ is exclusive or, and the input restriction $c\wedge d=0$ excludes conflicting commands. The output is the current stored $z$.

When armed, a sampled $c=1$ toggles $z$ and clears $e$. Further $c$ samples leave the output unchanged. A sampled $d=1$ sets $e=1$ without changing $z$, allowing a later $c$ to toggle it again. The same clock edge cannot both rearm and trigger because $c,d$ are never simultaneously high. Thus the first $c$ toggles from zero to one, and subsequent toggles each require a new $d$ followed by a later $c$.

Share the input-history bits of (a) between a high-run detector and a low-run detector. With $p,q$ the two preceding input samples, putThese detector outputs are mutually exclusive. Feed them into (b). An explicit four-bit synchronous sequential circuit, with initial state $(p,q,e,z)=(0,0,1,0)$, isEvery right-hand side uses the old state and the current input. In particular, the run detectors' combinational outputs are sampled by the toggle module at that same edge; there is no extra pipeline stage.

The first three consecutive high samples make $c=1$ at the third edge, toggling $z$ and clearing $e$. Continuing high input cannot toggle it again. Only three consecutive low samples can make $d=1$ and rearm it; interrupted low runs do not suffice. After rearming, a new three-sample high run produces the next toggle. This proves the debounced toggle switch behaviour, including rejection of short high and low disturbances.

The data input must remain stable for a specified interval before the sampling clock edge and a specified interval after it. Violations can prevent a well-defined sampled bit.

A synchronous sequential circuit stores a finite collection of bits $s$, reads inputs $a$, and updates all stored bits at each clock edge according to a specified next-state function $F$. A combinational output is $G(s,a)$; an output that is itself stored is included among the state bits. An initial state is part of a complete design. These equations provide a precise implementation-level description of a finite-state machine without requiring a particular gate drawing.

Store the two previous input bits in $p,q$. At the next clock edge, use $w=a\wedge p\wedge q$ and update $(p,q{)}^{\prime }=(a,p)$. The output is high exactly when the present input and previous two samples are all high. Replacing each input by its negation detects a three-sample low run. Both detectors can share the same two history bits, using $a\wedge p\wedge q$ and $\neg a\wedge \neg p\wedge \neg q$. With initial history zero, the high detector cannot trigger before three actual high samples have occurred.