Past exam of the year 1 of the computer science course of the University of Oxford / 2015 / Digital systems, linear algebra, introduction to formal proof (resit) / 2

For a CMOS inverter, connect one PMOS transistor from the positive supply $V_{DD}$ to the output and one NMOS transistor from the output to ground; drive both gates with the input $x$. When $x=0$, the PMOS transistor conducts and the NMOS transistor is off; when $x=1$, the reverse holds. Thus the output is $\neg x$, using two transistors.

For a four-input NAND gate, use four NMOS transistors in series between the output and ground, with gates $a,b,c,d$. Use four PMOS transistors in parallel between $V_{DD}$ and the output, with the same gate signals. The pull-down network conducts exactly when all four inputs are one; the pull-up network conducts whenever at least one input is zero. HenceAs usual for static CMOS, tie the NMOS transistor bodies to ground and the PMOS transistor bodies to $V_{DD}$.

Each parenthesized pair in the given Boolean function tests equality of two input bits:This is logical equivalence, or the two-input XNOR gate function. Thus $z$ is one whenever either input pair agrees. Generate the four complemented inputs with four inverters, and define the following NAND gate outputs:Feed these four outputs into a single four-input NAND gate. De Morgan's laws giveHere juxtaposition denotes logical conjunction. The construction uses only inverters, two-input NAND gates and one four-input NAND gate, as required.

The four CMOS inverters use $4\cdot 2$ transistors, the four two-input NAND gates use $4\cdot 4$, and the four-input NAND gate uses $8$. Therefore this particular design uses

A more economical static CMOS design follows from factoring the condition for $z=0$. The output is low exactly when both input pairs disagree:Generate $\neg a,\neg b,\neg c,\neg d$ with four CMOS inverters. Write $n(x)$ or $p(x)$ for an NMOS transistor or PMOS transistor whose gate receives $x$. In the following network expressions, a dash means a series connection and $\parallel$ means a parallel connection.

Connect this eight-device pull-down network between $z$ and ground:The first parallel module conducts exactly when $a\ne c$ and the second exactly when $b\ne d$. Their series connection therefore conducts precisely when $z$ should be zero.

By complementary CMOS network duality, connect this eight-device pull-up network between $V_{DD}$ and $z$:A PMOS transistor conducts when its gate is zero. Consequently the first upper branch conducts when $(\neg a\vee c)\wedge (a\vee \neg c)$, namely $a=c$; the second conducts when $b=d$. Their parallel connection gives the required logical disjunction. For every stable binary input, exactly one of the pull-up network and pull-down network conducts.

The figure labels each MOSFET channel by its gate signal; the four input CMOS inverters are additional to the devices drawn.

The custom CMOS circuit uses eight NMOS transistors and eight PMOS transistors in the output networks, plus eight transistors in the four input CMOS inverters:The complementary types give an actively driven output at either supply rail. An NMOS transistor provides a strong connection to ground; a PMOS transistor provides a strong connection to $V_{DD}$. An NMOS transistor used alone to pass a high level loses gate overdrive as the output rises, giving a threshold-degraded high level; the complementary problem affects a PMOS transistor passing a low level. Complementary networks avoid these degraded levels and, ideally, have no direct supply-to-ground conducting path for a stable input. Physical leakage and switching current remain, but a resistive load and its continuous static current are unnecessary.