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The capacitive bridging complex-error bandwidth is the largest frequency over which a receiving port preserves the source phasor within a specified complex relative gain error. The criterion includes phase shift as well as amplitude. A large DC input impedance alone cannot establish this bandwidth when input capacitance matters. The manufacturer's input models explicitly include resistive and capacitive paths.^[ref]

For the scalar impedance bridging with capacitive input model, assume a positive real source electrical resistance $R_s$, receiver resistance $R_{\mathrm{in}}>0$, and input capacitance $C_{\mathrm{in}}>0$ in parallel. Let $V_s$ be the unloaded source phasor. A voltage divider givesFor tolerance $0<\eta <1$, the complex relative gain error isIts square is strictly increasing in $x^2$, since its derivative is $(1+2g)/[(1+g{)}^2+x^2{]}^2>0$. Thus satisfying $E(f)\le \eta$ defines a continuous frequency interval starting at DC, whenever it is feasible. Rearranging givesThe DC error floor is ${\eta }_0=g/(1+g)$. If $\eta <{\eta }_0$, no frequency meets the tolerance; if $\eta ={\eta }_0$, only DC does. The boxed positive bandwidth applies when $\eta >{\eta }_0$.

For an original near-limit example, choose $R_s=10\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$. Then $g=0.01$ and the DC error is about 0.9901 percent. A 1 percent full-complex tolerance leaves onlyAn amplitude-only 1 percent criterion, $|H|\ge 0.99$, instead allows about $2273.47\mathrm{Hz}$. The half-power (approximately $-3\mathrm{dB}$) signal bandwidth, relative to DC, is $(1+g)/(2\pi R_s{C}_{\mathrm{in}})\approx 160.75\mathrm{kHz}$. These are three distinct specifications of this same ideal model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor follows by factoring the numerator:For fixed $g>0$ and $\eta \downarrow {\eta }_0$,This asymptotic equivalence explains the sharp loss of usable bandwidth when the resistive divider has already consumed nearly all the error allowance. Increasing $R_{\mathrm{in}}$ or reducing $R_s$ changes that floor; reducing only $C_{\mathrm{in}}$ rescales a feasible bandwidth but cannot remove infeasibility at DC.

The criterion also controls a complete waveform. Suppose a source waveform $v_s$ is both a square-integrable function and a bandlimited function, with spectrum supported where $|H-1|\le \eta$. For the corresponding zero-state response $v_L$, the Fourier transform of $v_L-v_s$ is $(H-1){\hat{v}}_s$. The Plancherel theorem, or the norm bound for a Fourier multiplier on L2, givesHere the Fourier transform uses the frequency-in-hertz convention, so the displayed Plancherel theorem has no extra normalization factor. This bound includes waveform changes caused by phase. It applies to the zero-state response of the stated frequency response. Any additional homogeneous solution from initially stored energy contributes its own error.

A bench check therefore needs both amplitude ratio and phase shift, with probe and cable capacitance included in the port model. Magnitude-only observations determine $|H|$ without determining $|1-H|$. The formula describes this chosen passive input network; additional amplifier dynamics require their own transfer function.

Impedance bridging with capacitive input treats a receiver's input as a resistance in parallel with a capacitance. Even when its DC input impedance is large, the capacitive path can draw appreciable electric current at higher frequency, changing both the amplitude and phase of the observed electric potential difference.

For source resistance $R_s$, receiving resistance $R_{\mathrm{in}}$ and input capacitance $C_{\mathrm{in}}$, use sinusoidal steady-state phasors and a linear source model. The receiving electrical admittance is $1/R_{\mathrm{in}}+\mathrm{i}\omega C_{\mathrm{in}}$, soHere $V_s$ is the open-circuit source phasor; $V_L$ is the loaded terminal phasor. The impedance bridging objective is $H$ near one, rather than merely a large quoted DC input resistance.

The amplitude and phase responses areAn amplitude-only tolerance and a tolerance on the full complex number express different requirements. The latter measuresFor positive resistances, capacitance and a chosen $0<\eta <1$, the capacitive bridging complex-error bandwidth condition $|1-H|\le \eta$ requiresA negative numerator means even the DC loading error exceeds the tolerance.

In an original example, $R_s=1\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$ give $g=0.001$. A one-percent complex-error tolerance permits frequencies only up to about $15.9\mathrm{kHz}$. At $100\mathrm{kHz}$ the amplitude ratio remains about $0.997$, but the phase is about $-3.59^{\circ }$ and the complex error about $0.0627$. A small amplitude error can coexist with a materially larger waveform-phase error.

High-input-impedance buffers are motivated by just this source-loading problem. Texas Instruments' three-amplifier presentation shows how current drawn from a source with finite output impedance degrades accuracy and how input buffers reduce loading.^[ref] The chosen component values above are not specifications of a particular amplifier. A real receiver may require additional input paths, frequency-dependent source impedance and a model of the connected cable or probe.

Input capacitance describes the capacitive part of an electrical port's small-signal input impedance, under stated bias, frequency, and termination conditions. In a simple parallel model with the $e^{i\omega t}$ convention, its electrical admittance isThe electric current drawn by the capacitance grows with angular frequency even if the DC input resistance is enormous. Analog Devices distinguishes differential input paths from common-mode paths to ground: a quoted capacitance must identify which terminals are driven and how the remaining circuit is connected.^[ref]

For an original loading example, let $R_{\mathrm{in}}=10\mathrm{M\Omega }$ and $C_{\mathrm{in}}=20\mathrm{pF}$. At $10\mathrm{MHz}$, the capacitive reactance magnitude is only $1/(2\pi f{C}_{\mathrm{in}})\approx 796\Omega$. A source with electrical resistance $R_s=1\mathrm{k\Omega }$ therefore has loaded-to-unloaded phasor ratioThe DC ratio is about $0.99990$. Thus a resistance-only reading would miss a substantial high-frequency amplitude reduction. The numbers are chosen examples, not a specification for a named device.

For this same model, the source-to-input time constant is $(R_s\Vert R_{\mathrm{in}})C_{\mathrm{in}}$ and the DC-normalized half-power signal bandwidth is its reciprocal divided by $2\pi$. A complex-error requirement is instead governed by capacitive bridging complex-error bandwidth; these specifications answer different questions.

For input capacitance inferred from measured admittance, apply a small sinusoidal electric potential difference, measure the input electric current and its phase shift, and infer $\mathrm{Im}(I/V)/\omega$ within the parallel-capacitance approximation. Fixture, cable, and probe capacitances contribute to the measured port unless removed or included explicitly. Dependence on bias or frequency can make a single fitted $C_{\mathrm{in}}$ an inadequate model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor describes how the usable frequency interval disappears when a resistive divider has almost exhausted a complex-error allowance. Use the model and exact formula in capacitive bridging complex-error bandwidth: $g=R_s/R_{\mathrm{in}}>0$, ${\tau }_s=R_s{C}_{\mathrm{in}}$, and the DC floor ${\eta }_0=g/(1+g)$. Write the available extra tolerance as $\Delta =\eta -{\eta }_0>0$. The exact bandwidth becomesAt fixed positive $g$, the leading numerator is linear in $\Delta$, so $f_{\eta }$ is proportional to $\sqrt{\Delta }$. Thus demanding four times less extra tolerance approximately halves the bandwidth; it does not reduce it by a factor of four.

For an original example, choose $R_s=20\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$, and $C_{\mathrm{in}}=50\mathrm{pF}$. Then $g=0.02$, ${\tau }_s=1\mu \mathrm{s}$, and ${\eta }_0\approx 0.019608$. Taking $\Delta =0.00020$ gives about $456\mathrm{Hz}$ from the exact formula. Taking $\Delta =0.00005$ gives about $228\mathrm{Hz}$. The small deviation from an exact two-to-one ratio comes from the retained quadratic term and denominator.

The qualification fixed positive $g$ matters. If the receiving resistance is infinite, $g={\eta }_0=0$ andwhich is linear in small $\eta$. For a small but nonzero floor, the square-root approximation needs $\Delta$ small compared with ${\eta }_0$ as well as with the remaining distance to unit error. The crossover from square-root to linear capacitive bridging bandwidth scaling prevents using the fixed-floor asymptotic expression uniformly as $g$ also tends to zero.

This is a limit of the chosen passive input impedance model, not an empirical limit for every amplifier. The manufacturer's shunt-capacitance model motivates the resistive/capacitive paths; an actual bench comparison must include both amplitude and phase shift and the probe's added capacitance.^[ref]