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One complete repetition of a periodic clock signal, for example from one rising clock edge to the next. Its duration is the clock period. A synchronous sequential circuit can update its stored state once per designated clock edge; a one-cycle output pulse remains asserted for one such interval.

Enter a distinguished Moore machine state whose output is active, and ensure that every outgoing transition leaves that state for an inactive-output state. The output then lasts one clock period. Its outgoing transitions may simultaneously recognize the start of the next event, avoiding an unnecessary idle cycle. The one-period statement refers to the synchronous logical model, with ordinary propagation delay after each clock edge.

A temporary excursion of an output logic signal to its active level. A clocked controller may specify the duration in complete clock periods, rather than relying on an analogue delay.

Use a three-state Moore machine for a rearmable one-cycle pulse generator. Call the states Ready, Pulse, and Wait. Their outputs are respectively $z=0,1,0$, and initialize in Ready. Labels below are the sampled input pair ab; because simultaneous ones are unspecified, choose reset priority for 11.

The complete chosen state transition table is

A sampled trigger 10 causes a pulse only in Ready. Leaving Pulse unconditionally on the next edge keeps its output high for exactly one clock period, even if a remains high. In Wait, further triggers are ignored until a sampled reset rearms the finite-state machine.

The crucial transition is Pulse --01--> Ready. If reset occurs in the cycle immediately following a trigger, this transition both ends the current pulse and rearms the circuit. The next trigger then produces a pulse after just one intervening low-output cycle. Sending every exit from Pulse to Wait would lose that reset and fail the alternate-cycle requirement. This behavior is explicitly visible in the last three pulses of the original timing diagram.^[ref]

For the sixteen sampled pairs in that diagram, numbering the first edge as 1, z is high just after edges $2,10,13,15$ and low after every other edge. Equivalently,The two low-output states cannot be merged: the same future trigger must produce a pulse from Ready and be ignored from Wait. A separate high-output state is needed to hold the one-cycle pulse, explaining the three-state design.

A D flip-flop stores one bit. At its specified active clock edge, it samples $D$ and, after its clock-to-Q delay, makes $Q$ equal to that sampled value. Between active clock edges it retains the stored value. The input must meet the setup and hold time requirements around the sampling edge; a level-sensitive latch would have different behavior.

For a finite-state sequential circuit, encode the present state in a bank of D flip-flops. Feed their outputs $q$ and the external inputs $u$ to combinational logic computing the next-state function $F(q,u)$, and connect those outputs to the flip-flop $D$ inputs. A common clock signal then performs the simultaneous updateOutput combinational logic computes $H(q)$ for a Moore machine or $H(q,u)$ for a Mealy machine. Since any finite next-state and output table is a Boolean function, it has a Boolean circuit implementation. Initialization specifies the starting state, and unused state encodings require either a recovery rule or an initialization assumption. The clock period must accommodate propagation through the D flip-flops and intervening combinational logic before the next sampling edge.

Use a synchronous binary counter with three positive-edge-triggered D flip-flops, all driven by the same clock signal. Write their outputs $q_2{q}_1{q}_0$, with $q_0$ the least significant bit. The next-state Boolean functions areImplement these with one NOT gate, two exclusive or gates, and one AND gate. Connect each $D_i$ to its corresponding D flip-flop; its output $q_i$ is address line $i$. A reset input clears all three flip-flops to zero, so the first selected sensor is sensor zero.

The state sequence isThe low bit toggles at every clock edge, the middle bit toggles exactly when the old low bit is one, and the high bit toggles exactly when both old lower bits are one. These are precisely the carry conditions for incrementing a three-bit binary representation. Every possible state belongs to the cycle, so there is no unused state requiring recovery. Choose a clock period allowing the combinational logic to settle before the next capture.

Use eight parallel 8:1 multiplexers and one shared three-bit binary counter. If $d_{i,j}$ is bit $j$ from sensor $i$, connect $d_{0,j},\dots ,d_{7,j}$ to multiplexer $j$. Connect all selection inputs to the binary counter outputs. Then data line $j$ carries $d_{q,j}$, so all eight data lines belong to the same selected sensor. Send the three counter outputs to the receiver as the address lines as well.

After reset the receiver sees sensors $0,1,\dots ,7,0,\dots$, one per clock period. Sample the data and address only after the binary counter and multiplexers have settled, for example on the opposite clock edge with a sufficiently long clock period. Changing addresses can otherwise cause transient logic hazards. The transmitter uses eleven signal lines, apart from any shared clock or reset connection.

Use an eight-bit modulo-256 binary counter, eight 256:1 multiplexers, eight data lines and eight address lines. Thus there are sixteen signal lines, apart from clock and reset, and a full scan takes 256 clock periods. The counter next-state equations generalize toA 256:1 multiplexer for one data bit can be made hierarchically: 32 first-stage 8:1 multiplexers select within eight-sensor groups using $q_2{q}_1{q}_0$; four second-stage 8:1 multiplexers select groups using $q_5{q}_4{q}_3$; one final 4:1 multiplexer selects using $q_7{q}_6$. A final 8:1 multiplexer also works if one select input is fixed to zero and only four data inputs are used. Repeat this network eight times, sharing all selection lines. Allow for the extra propagation delay when choosing the clock period.