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An integrated circuit technology using complementary MOSFETs. CMOS names a circuit technology; active-pixel sensor names a detector architecture.

Current-polarity dead-time compensation adjusts a switching command to oppose the dead-time output-voltage error predicted from the direction of load electric current. During bridge switching dead time, an inductive current can flow through a MOSFET body diode; the resulting rail clamp makes the cycle-average error depend on current direction. The manufacturer’s bridge-state diagrams establish that current-path mechanism.^[ref]

Consider an original ideal half-bridge model with rail separation $V_d$, switching period $T$, duty fraction $D$, and effective dead-time fraction $\delta =t_d/T$. Assume current has one nonzero sign throughout the affected interval and that device drops are negligible. Let positive current leave the midpoint, so that the adopted clamping model givesFor a desired normalized average $D_{\ast }$, chooseSubstitution cancels the average error in this model. The correction changes the commanded pulse duration; it does not remove the nonoverlap needed to avoid H-bridge shoot-through. Different full-bridge switching patterns require applying the appropriate event model to each leg before subtracting the terminal averages.

For $V_d=48\mathrm{V}$, $T=50\mu \mathrm{s}$ and $t_d=0.5\mu \mathrm{s}$, $\delta =0.01$ and the uncompensated error magnitude is $0.48\mathrm{V}$. At $D_{\ast }=0.40$, use $D_{\mathrm{cmd}}=0.41$ for positive current and $0.39$ for negative current. Each gives the intended $19.2\mathrm{V}$ average under the stated assumptions.

Command limits matter. Suppose the allowed duty range ends at $0.98$ because a minimum off-time is required. With positive current and $D_{\ast }=0.975$, the formula asks for $0.985$. Clipping to $0.98$ leaves an actual normalized average of $0.97$, an error of $-0.24\mathrm{V}$ at this bus potential difference. Thus a compensation law can be correct locally while the requested average lies outside its achievable range. Minimum pulse durations impose further limits.

Current-sign uncertainty in dead-time compensation is particularly important near a zero crossing. If an estimated sign $\hat{\sigma }$ is used while the actual sign is $\sigma$, the residual error, before command clipping, isA wrong opposite sign doubles the uncompensated error magnitude: $0.96\mathrm{V}$ in the example. Current-sensor delay, noise and a sign reversal within the switching interval can all invalidate a sign held constant for the cycle. Using a zero correction in an uncertain interval avoids that particular wrong-sign doubling, but does not cancel the original error.

A proposed bench comparison records gate commands, midpoint electric potential difference and load electric current together, then integrates each switching cycle with and without compensation. Compare positive-current, negative-current and crossing intervals separately, and repeat near pulse limits. This separates the average-error cancellation being tested from preservation of nonoverlap, device voltage drops and imperfect knowledge of switching delay.

An ideal insulating gate blocks particle exchange between the gate and substrate of a MOSFET. Their electrochemical potentials, represented by their band-diagram Fermi levels, therefore need not coincide. An applied gate voltage fixes their difference; with $e>0$ and voltage defined by an electron reservoir, ${\tilde{\mu }}_g-{\tilde{\mu }}_s=-e{V}_g$. Contact work-function differences also affect band bending, so equal Fermi levels do not imply flat bands. Each conducting region can separately have a spatially constant equilibrium electrochemical potential.

Hector Hernandez is the credited presenter and preparer of the TI Precision Labs training material Brushed DC Motor 2: The H-Bridge by Hector Hernandez. Its scientific subject is the H-bridge: a switching network that applies either polarity to a motor and provides paths for the electric current already stored in the inductive load. The primary title slide gives his name exactly as used here.^[ref]

The material connects a controller's commands to MOSFET gate drive, then distinguishes forward/reverse conduction from recirculation. That distinction matters because reversing a command does not instantaneously reverse the electric current in a motor's inductance. Slides 5–7 show electric current decay paths through diodes or conducting switches.^[ref]

For an original bridge-loss example, take a $12\mathrm{V}$ supply and a stated operating electric current of $2\mathrm{A}$ through two conducting switches, each with electrical resistance $0.05\Omega$. Their combined conduction loss isand their combined potential drop is $2IR=0.20\mathrm{V}$. The motor terminals receive $11.8\mathrm{V}$ in the chosen conducting state, giving $23.6\mathrm{W}$ of electrical input from $24\mathrm{W}$ supplied. This is not a calculation of mechanical output: motor winding loss, induced electric potential difference and mechanical losses remain separate.

A bench comparison records terminal electric potential difference and motor electric current together while changing the bridge state. The waveforms separate voltage reversal from electric current reversal and expose the recirculation interval discussed in the training material. The numerical values above are illustrative calculations, not performance measurements attributed to Hernandez.

For an n-channel MOSFET, assume a gradual channel, constant charge carrier mobility $\mu$, gate capacitance per area $C_{\mathrm{ox}}$, width $W$ and length $L$. With overdrive $V_{\mathrm{ov}}=V_{GS}-V_T>0$, the inversion-sheet charge magnitude is $C_{\mathrm{ox}}(V_{\mathrm{ov}}-V(x))$. The drift-current relation $I_D=\mu W{C}_{\mathrm{ox}}(V_{\mathrm{ov}}-V)V^{\prime }$ is constant along the channel. Integrating from $V=0$ to $V_{DS}$ over length $L$ proves the displayed expression for $0\le V_{DS}\le V_{\mathrm{ov}}$. At the drain pinch-off condition $V_{DS}=V_{\mathrm{ov}}$, it yields $I_{D,\mathrm{sat}}=\mu C_{\mathrm{ox}}W{V}_{\mathrm{ov}}^2/(2L)$. This ideal saturation neglects channel-length modulation and short-channel velocity saturation.

For an ideal MOSFET with a nondegenerate p-type semiconductor of acceptor density $N_A$, define ${\varphi }_F=(k_{B}T/e)\ln (N_A/n_i)>0$, where $n_i$ is the intrinsic carrier concentration. A positive surface electric potential ${\psi }_s$ lowers the local conduction band and valence band by $e{\psi }_s$. The surface electron density is $n_s=(n_i^2/N_A)\exp (e{\psi }_s/k_{B}T)$. Equality $n_s=N_A$ gives the conventional onset of strong inversion at ${\psi }_s=2{\varphi }_F$. The earlier crossover $n_s=p_s=n_i$ occurs at ${\psi }_s={\varphi }_F$. Neither condition requires the Fermi level to enter the conduction band.

A MOSFET is a voltage-controlled three-terminal switch: the insulated gate controls a conductive channel, giving high input impedance and useful current gain at the circuit level. A CMOS inverter actively restores either logic rail, has voltage gain near its switching threshold, and ideally draws no static supply current in either settled logic state. Real devices have leakage and consume energy while switching.

A single p-n junction is a two-terminal diode; its current is controlled by its own terminal voltage, so it does not by itself provide an independently controlled switch, gain and restoring inversion. Cross-coupled CMOS inverters form a bistable memory element. A lone inverter is not itself a complete memory cell, and a p-n junction can still serve useful rectification or capacitance functions.

The left transistor is an n-channel MOSFET in a p-type silicon substrate; the right is a p-channel MOSFET in an n-well. The region assignments are:

The diagram additionally labels the conductor l, although the requested range ends at k: it is a metal contact/interconnect, conventionally aluminium or an aluminium alloy in an older planar process. Modern processes can use metal gates, high-permittivity gate dielectrics and different interconnect stacks; these are alternatives, not evidence that the illustrated conventional gate is aluminium.

For a CMOS inverter, join h and j to the input and d and e to the output. Connect f and g to $V_{\mathrm{DD}}$, and b and c to ground; these ties keep the body junctions appropriately biased.

An n-channel MOSFET has two heavily n-doped source and drain regions in a p-type body, with an insulated gate above the intervening surface. A positive gate voltage first depletes surface electron holes and then induces an electron semiconductor inversion layer. Above threshold $V_T$ this layer connects source to drain. Gate voltage controls the channel charge through the oxide capacitance, while the insulating gate permits a very small steady gate current.

For the long-channel MOSFET current law, let $C_{\mathrm{ox}}$ be oxide capacitance per area, $W,L$ channel width and length, and use constant mobility ${\mu }_n$. In the gradual-channel approximation,At larger drain voltage the ideal channel pinches off near the drain and the current saturates atCarriers still flow through the pinch-off region; pinch-off does not mean zero drain current. These formulas neglect channel-length modulation, short-channel effects and velocity saturation. A p-channel device reverses the carrier type and operating polarities. Gate control makes MOSFETs useful as electronic switches and amplifiers.

A field-effect transistor uses a gate voltage to control the conducting channel between source and drain. In a MOSFET, the gate is insulated from the semiconductor: an electric field changes the channel carrier population with little steady gate current. An n-channel device creates an semiconductor inversion layer when the gate sufficiently attracts electrons to a p-type surface. The drain supply provides the output power; the gate controls that flow.

The long-channel MOSFET current law follows from the gradual-channel approximation. With gate capacitance per area $C_{\mathrm{ox}}$, threshold voltage $V_T$, channel width $W$, length $L$, constant charge carrier mobility $\mu$ and $V_{mov}=V_{GS}-V_T>0$, the local sheet charge magnitude is $C_{\mathrm{ox}}(V_{mov}-V(x))$. Integrating the drift current along the channel givesAt $V_{DS}=V_{mov}$, the drain end reaches pinch-off. The ideal long-channel saturation current is $I_D=\mu C_{\mathrm{ox}}W{V}_{mov}^2/(2L)$; this assumes negligible channel-length modulation. A junction field-effect transistor instead changes the channel width through a reverse-biased depletion region.

Experimentally, measure $I_D$ against $V_{GS}$ at fixed drain bias to see gate control, and against $V_{DS}$ at several fixed gate biases to distinguish the approximately linear and saturation regimes. Simultaneously checking gate leakage tests the insulated-gate assumption.

A positive gate voltage attracts electrons towards the oxide interface of the p-type semiconductor and repels mobile electron holes. The uncovered ionized acceptors form a negatively charged depletion region. Increasing the voltage further creates a thin electron-rich semiconductor inversion layer at the surface. The conduction band and valence band both bend downwards towards the positively biased gate, because an electron's electrostatic energy is $-e\psi$.

In an ideal nondegenerate substrate with acceptor density $N_A$, write ${\varphi }_F=(k_{B}T/e)\ln (N_A/n_i)>0$ and surface potential ${\psi }_s$ relative to the neutral bulk. The electron and hole surface densities areThe first change of majority-carrier type occurs at ${\psi }_s={\varphi }_F$, where $n_s=p_s=n_i$. The conventional MOS inversion threshold for appreciable strong inversion isAt threshold the inversion sheet is just developing, while a much thicker depletion region lies between it and the neutral p-type bulk. Inversion does not require the conduction band to cross the Fermi level: the surface can remain nondegenerate.

The metal and semiconductor Fermi levels need not be equal. The ideal oxide blocks particle exchange, so the gate and substrate can maintain different electrochemical potentials. In a biased MOSFET, the gate-to-substrate Fermi-level difference is ${\tilde{\mu }}_g-{\tilde{\mu }}_s=-e{V}_g$, when the applied voltage is defined in the electron-reservoir convention. Each region can separately be in internal equilibrium. If an external zero-voltage connection instead equilibrates the reservoirs, their Fermi levels coincide, but different work functions can still cause band bending. Here the chemical potential shown in a band diagram is the electron electrochemical potential; the purely chemical contribution alone is not the equilibrium criterion for charged particles.

A more economical static CMOS design follows from factoring the condition for $z=0$. The output is low exactly when both input pairs disagree:Generate $\neg a,\neg b,\neg c,\neg d$ with four CMOS inverters. Write $n(x)$ or $p(x)$ for an NMOS transistor or PMOS transistor whose gate receives $x$. In the following network expressions, a dash means a series connection and $\parallel$ means a parallel connection.

Connect this eight-device pull-down network between $z$ and ground:The first parallel module conducts exactly when $a\ne c$ and the second exactly when $b\ne d$. Their series connection therefore conducts precisely when $z$ should be zero.

By complementary CMOS network duality, connect this eight-device pull-up network between $V_{DD}$ and $z$:A PMOS transistor conducts when its gate is zero. Consequently the first upper branch conducts when $(\neg a\vee c)\wedge (a\vee \neg c)$, namely $a=c$; the second conducts when $b=d$. Their parallel connection gives the required logical disjunction. For every stable binary input, exactly one of the pull-up network and pull-down network conducts.

The figure labels each MOSFET channel by its gate signal; the four input CMOS inverters are additional to the devices drawn.

Klaus von Klitzing, G. Dorda and M. Pepper reported a silicon MOSFET measurement in 1980. Its gate controlled an semiconductor inversion layer; transverse contacts measured the Hall voltage and separate longitudinal contacts measured dissipation. One sweep held $B=18\mathrm{T}$, $T=1.5\mathrm{K}$ and $I=1\mu \mathrm{A}$ fixed while varying gate voltage. Hall plateaus accompanied small longitudinal voltages. Device-geometry comparisons and high-input-impedance voltage measurements helped test whether contact placement or electrical loading produced the result.^[ref]

This original functional diagram separates transverse and longitudinal readouts; it does not reproduce the historical device's dimensions. The gate inset explains how a field-effect transistor provides an adjustable two-dimensional electron gas. A longitudinal voltage close to zero is a useful check because accidental longitudinal separation between Hall contacts can otherwise contaminate the transverse measurement.