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The capacitive bridging complex-error bandwidth is the largest frequency over which a receiving port preserves the source phasor within a specified complex relative gain error. The criterion includes phase shift as well as amplitude. A large DC input impedance alone cannot establish this bandwidth when input capacitance matters. The manufacturer's input models explicitly include resistive and capacitive paths.^[ref]

For the scalar impedance bridging with capacitive input model, assume a positive real source electrical resistance $R_s$, receiver resistance $R_{\mathrm{in}}>0$, and input capacitance $C_{\mathrm{in}}>0$ in parallel. Let $V_s$ be the unloaded source phasor. A voltage divider givesFor tolerance $0<\eta <1$, the complex relative gain error isIts square is strictly increasing in $x^2$, since its derivative is $(1+2g)/[(1+g{)}^2+x^2{]}^2>0$. Thus satisfying $E(f)\le \eta$ defines a continuous frequency interval starting at DC, whenever it is feasible. Rearranging givesThe DC error floor is ${\eta }_0=g/(1+g)$. If $\eta <{\eta }_0$, no frequency meets the tolerance; if $\eta ={\eta }_0$, only DC does. The boxed positive bandwidth applies when $\eta >{\eta }_0$.

For an original near-limit example, choose $R_s=10\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$ and $C_{\mathrm{in}}=100\mathrm{pF}$. Then $g=0.01$ and the DC error is about 0.9901 percent. A 1 percent full-complex tolerance leaves onlyAn amplitude-only 1 percent criterion, $|H|\ge 0.99$, instead allows about $2273.47\mathrm{Hz}$. The half-power (approximately $-3\mathrm{dB}$) signal bandwidth, relative to DC, is $(1+g)/(2\pi R_s{C}_{\mathrm{in}})\approx 160.75\mathrm{kHz}$. These are three distinct specifications of this same ideal model.

The square-root collapse of capacitive bridging bandwidth near the DC error floor follows by factoring the numerator:For fixed $g>0$ and $\eta \downarrow {\eta }_0$,This asymptotic equivalence explains the sharp loss of usable bandwidth when the resistive divider has already consumed nearly all the error allowance. Increasing $R_{\mathrm{in}}$ or reducing $R_s$ changes that floor; reducing only $C_{\mathrm{in}}$ rescales a feasible bandwidth but cannot remove infeasibility at DC.

The criterion also controls a complete waveform. Suppose a source waveform $v_s$ is both a square-integrable function and a bandlimited function, with spectrum supported where $|H-1|\le \eta$. For the corresponding zero-state response $v_L$, the Fourier transform of $v_L-v_s$ is $(H-1){\hat{v}}_s$. The Plancherel theorem, or the norm bound for a Fourier multiplier on L2, givesHere the Fourier transform uses the frequency-in-hertz convention, so the displayed Plancherel theorem has no extra normalization factor. This bound includes waveform changes caused by phase. It applies to the zero-state response of the stated frequency response. Any additional homogeneous solution from initially stored energy contributes its own error.

A bench check therefore needs both amplitude ratio and phase shift, with probe and cable capacitance included in the port model. Magnitude-only observations determine $|H|$ without determining $|1-H|$. The formula describes this chosen passive input network; additional amplifier dynamics require their own transfer function.

The crossover from square-root to linear capacitive bridging bandwidth scaling occurs when excess error allowance becomes comparable with the resistive error floor itself. In square-root collapse of capacitive bridging bandwidth near the DC error floor, put ${\eta }_0=g/(1+g)$, $g=R_s/R_{\mathrm{in}}$, $\Delta =\eta -{\eta }_0>0$, and ${\tau }_s=R_s{C}_{\mathrm{in}}$. For positive ${\eta }_0$, introduce the dimensionless ratio $\xi =\Delta /{\eta }_0$. The exact bandwidth can then be writtenThis single expression distinguishes the two regimes without exchanging small-parameter limits silently.

When $\Delta \ll {\eta }_0$ and the tolerance is away from one, the factor $\sqrt{\xi (2+\xi )}$ is approximately $\sqrt{2\xi }$: bandwidth scales as $\sqrt{\Delta }$. When ${\eta }_0\ll \Delta \ll 1$, that factor is approximately $\xi$, while the denominator is close to one: bandwidth is approximately $(1+g)\Delta /(2\pi {\tau }_s)$. The exactly zero-floor model has the corresponding small-tolerance linear behavior.

For an original dimensionless comparison, take ${\eta }_0=10^{-4}$. At $\xi =0.01$, replacing $\sqrt{\xi (2+\xi )}$ by $\sqrt{2\xi }$ changes the numerator by only about $0.25\%$. At $\xi =100$, replacing it by $\xi$ changes the numerator by about $1\%$; here the total tolerance is $0.0101$, so the denominator differs little from one. The tolerance is small in both cases, but a different approximation is useful because its size relative to the floor differs.

In component terms, increasing $R_{\mathrm{in}}$ moves the crossover by lowering ${\eta }_0$; changing only $C_{\mathrm{in}}$ rescales the frequency axis through ${\tau }_s$. A sweep of receiving electrical resistance and input capacitance can therefore separate a floor effect from a frequency-scale effect. The resistive/shunt-capacitive manufacturer model motivates the apparatus assumptions.^[ref] The specification remains a full complex relative gain error, including phase shift, rather than only an amplitude or half-power threshold.

Input capacitance describes the capacitive part of an electrical port's small-signal input impedance, under stated bias, frequency, and termination conditions. In a simple parallel model with the $e^{i\omega t}$ convention, its electrical admittance isThe electric current drawn by the capacitance grows with angular frequency even if the DC input resistance is enormous. Analog Devices distinguishes differential input paths from common-mode paths to ground: a quoted capacitance must identify which terminals are driven and how the remaining circuit is connected.^[ref]

For an original loading example, let $R_{\mathrm{in}}=10\mathrm{M\Omega }$ and $C_{\mathrm{in}}=20\mathrm{pF}$. At $10\mathrm{MHz}$, the capacitive reactance magnitude is only $1/(2\pi f{C}_{\mathrm{in}})\approx 796\Omega$. A source with electrical resistance $R_s=1\mathrm{k\Omega }$ therefore has loaded-to-unloaded phasor ratioThe DC ratio is about $0.99990$. Thus a resistance-only reading would miss a substantial high-frequency amplitude reduction. The numbers are chosen examples, not a specification for a named device.

For this same model, the source-to-input time constant is $(R_s\Vert R_{\mathrm{in}})C_{\mathrm{in}}$ and the DC-normalized half-power signal bandwidth is its reciprocal divided by $2\pi$. A complex-error requirement is instead governed by capacitive bridging complex-error bandwidth; these specifications answer different questions.

For input capacitance inferred from measured admittance, apply a small sinusoidal electric potential difference, measure the input electric current and its phase shift, and infer $\mathrm{Im}(I/V)/\omega$ within the parallel-capacitance approximation. Fixture, cable, and probe capacitances contribute to the measured port unless removed or included explicitly. Dependence on bias or frequency can make a single fitted $C_{\mathrm{in}}$ an inadequate model.

Input capacitance inferred from measured admittance is a parameter estimate from the quadrature component of a specified electrical port's response. In the parallel model of input capacitance, write its electrical admittance as $Y=G+i\omega C$ with the $e^{i\omega t}$ convention. A small sinusoidal excitation and simultaneous input-current measurement giveBoth amplitude ratio and relative wave phase matter. The differential versus common-mode terminals and operating point conditions must be specified, as in the manufacturer's input-path diagrams.^[ref]

For an original error calculation, suppose the amplitude ratio is exact but the measured current-to-voltage wave phase has offset $\delta$. Then $Y_{\mathrm{meas}}=Y{e}^{i\delta }$ andThe phase calibration error in an admittance-based capacitance estimate can therefore mix a conductance term into the small capacitive estimate. For small $\delta$, the leading error is $(G/\omega )\delta$, not a fixed percentage of $C$.

Choose $G=10\mu \mathrm{S}$, $C=20\mathrm{pF}$, and $f=10\mathrm{kHz}$. The true susceptance is only $\omega C\approx 1.257\mu \mathrm{S}$. A one-degree wave phase offset yields $\hat{C}\approx 22.775\mathrm{pF}$, an error of about $13.9\%$, despite perfect amplitude readings. These are chosen port-model values, not measured device specifications.

A useful measurement repeats the estimate over frequency and excitation amplitude. A nearly constant fitted $C$ and a residual consistent with $G+i\omega C$ support the assumed model; they do not prove that all parasitic effects were removed. A known fixture admittance adds to a parallel port and must be subtracted or retained in the model. At very small susceptance, uncertainty in the relative wave phase can dominate, so a high DC input impedance alone is not evidence for a precise capacitance measurement.

Phase calibration error in an admittance-based capacitance estimate can rotate a large in-phase conductance into a small capacitive quadrature. In the parallel port model $Y=G+i\omega C$ with $G\ge 0$, $C>0$, and the $e^{i\omega t}$ convention, a relative wave phase error $\delta$ gives $Y_{\mathrm{meas}}=Y{e}^{i\delta }$. The exact estimate in input capacitance inferred from measured admittance therefore has relative errorThe ratio $G/(\omega C)$, not the DC resistance alone, determines sensitivity to a small wave phase rotation. The manufacturer's separate differential/common-mode port models motivate specifying the terminals and operating point before fitting an input capacitance.^[ref]

If $|\delta |\le ϵ\le \pi /2$, the worst absolute relative error is bounded byThe negative endpoint $\delta =-ϵ$ attains this bound. For target relative error $r>1-\cos ϵ$, a sufficient frequency condition isThis condition assumes the same $G+i\omega C$ model and the same phase-error bound remain valid over that frequency range.

For an original planning example, take $G=1\mu \mathrm{S}$, $C=50\mathrm{pF}$ and $ϵ=0.5^{\circ }$. The bound is about $2.782\%$ at $1\mathrm{kHz}$ and $0.282\%$ at $10\mathrm{kHz}$. A one-percent target requires approximately $f\ge 2.788\mathrm{kHz}$ in this model. Increasing frequency suppresses the conductance-mixing term, but leaves the $1-\cos ϵ$ term and can expose other unmodelled parasitic effects.

A measurement uses the same voltage/current wave phase reference for the ratio $I/V$, checks that reference with a known port, and retains fixture admittance in the model or subtracts a validated value. Amplitude measurement calibration alone cannot establish this wave phase bound. The numbers above are chosen calculations, not device specifications or a claim that a high-frequency measurement is automatically more accurate.

The square-root collapse of capacitive bridging bandwidth near the DC error floor describes how the usable frequency interval disappears when a resistive divider has almost exhausted a complex-error allowance. Use the model and exact formula in capacitive bridging complex-error bandwidth: $g=R_s/R_{\mathrm{in}}>0$, ${\tau }_s=R_s{C}_{\mathrm{in}}$, and the DC floor ${\eta }_0=g/(1+g)$. Write the available extra tolerance as $\Delta =\eta -{\eta }_0>0$. The exact bandwidth becomesAt fixed positive $g$, the leading numerator is linear in $\Delta$, so $f_{\eta }$ is proportional to $\sqrt{\Delta }$. Thus demanding four times less extra tolerance approximately halves the bandwidth; it does not reduce it by a factor of four.

For an original example, choose $R_s=20\mathrm{k\Omega }$, $R_{\mathrm{in}}=1\mathrm{M\Omega }$, and $C_{\mathrm{in}}=50\mathrm{pF}$. Then $g=0.02$, ${\tau }_s=1\mu \mathrm{s}$, and ${\eta }_0\approx 0.019608$. Taking $\Delta =0.00020$ gives about $456\mathrm{Hz}$ from the exact formula. Taking $\Delta =0.00005$ gives about $228\mathrm{Hz}$. The small deviation from an exact two-to-one ratio comes from the retained quadratic term and denominator.

The qualification fixed positive $g$ matters. If the receiving resistance is infinite, $g={\eta }_0=0$ andwhich is linear in small $\eta$. For a small but nonzero floor, the square-root approximation needs $\Delta$ small compared with ${\eta }_0$ as well as with the remaining distance to unit error. The crossover from square-root to linear capacitive bridging bandwidth scaling prevents using the fixed-floor asymptotic expression uniformly as $g$ also tends to zero.

This is a limit of the chosen passive input impedance model, not an empirical limit for every amplifier. The manufacturer's shunt-capacitance model motivates the resistive/capacitive paths; an actual bench comparison must include both amplitude and phase shift and the probe's added capacitance.^[ref]