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One complete repetition of a periodic clock signal, for example from one rising clock edge to the next. Its duration is the clock period. A synchronous sequential circuit can update its stored state once per designated clock edge; a one-cycle output pulse remains asserted for one such interval.

Clock frequency is the number of cycles of a clock signal per unit time. If its period is $T_c$, its frequency is $f=1/T_c$. A $3\times 10^9$ hertz clock has a nominal period of about $0.333\times 10^{-9}$ seconds. The clock coordinates timed operations; it does not specify how many complete program instructions are performed in each cycle.

For a fixed-frequency processor, execution time can be written as instruction count times average cycles per instruction divided by frequency. Raising frequency can improve that component of runtime, but it may also require a different pipeline organization or increase power and thermal constraints. Memory waits and dependencies can leave some cycles without completed instructions, while superscalar execution can complete several instructions in one cycle. Performance comparisons must therefore include the workload and microarchitecture, not only the clock rating.

The time between equivalent clock edges in consecutive cycles of a periodic clock signal. It is the reciprocal of the clock's frequency.

An electronic display cycling through the six die faces while a switch is pressed. A modulo-six counter and combinational logic can drive seven lights arranged as die pips. The apparent unpredictability comes from uncertainty in release timing relative to a rapid clock signal; deterministic cycling alone does not establish equal outcome probabilities.

A hardware timer uses a clock signal to measure intervals, commonly by a digital counter with capture or comparison facilities. A comparison event can request an interrupt or change an output directly. Counter resolution, wraparound, interrupt latency and the hardware's comparison semantics determine the timing guarantees available to software.

A fully synchronous sequential circuit has all its state stored in edge-triggered elements driven by a common clock signal, with combinational logic computing the next state from the current state and inputs. State updates occur together at the designated clock edges, rather than letting one register output serve as another register's ripple clock. Its ideal equations areFor a Moore machine the output function depends only on the state, $z_k=G(s_k)$. Physical design must leave enough time for register-to-register combinational paths and satisfy setup time and hold time at every receiving storage element.

A D flip-flop stores one bit. At its specified active clock edge, it samples $D$ and, after its clock-to-Q delay, makes $Q$ equal to that sampled value. Between active clock edges it retains the stored value. The input must meet the setup and hold time requirements around the sampling edge; a level-sensitive latch would have different behavior.

For a finite-state sequential circuit, encode the present state in a bank of D flip-flops. Feed their outputs $q$ and the external inputs $u$ to combinational logic computing the next-state function $F(q,u)$, and connect those outputs to the flip-flop $D$ inputs. A common clock signal then performs the simultaneous updateOutput combinational logic computes $H(q)$ for a Moore machine or $H(q,u)$ for a Mealy machine. Since any finite next-state and output table is a Boolean function, it has a Boolean circuit implementation. Initialization specifies the starting state, and unused state encodings require either a recovery rule or an initialization assumption. The clock period must accommodate propagation through the D flip-flops and intervening combinational logic before the next sampling edge.

A particularly transparent design uses six D flip-flops in a one-hot encoding. Let $Q_i=1$ mean that face $i$ is displayed. Initialize $Q_1=1$ and $Q_2=\cdots =Q_6=0$, and wire the next-state inputs as a ring:All six D flip-flops share the same active clock edge. Each pulse moves the single stored $1$ to the next position, giving the state-transition diagram cycle $1\to 2\to 3\to 4\to 5\to 6\to 1$. The representation invariant “exactly one $Q_i$ is high” holds after initialization and is preserved by rotation. Six D flip-flops are more than the three-bit theoretical minimum, but their simple wiring gives a complete implementation without requiring that minimum.

Decode the seven lamps by their positions, with $T,M,B$ denoting top, middle and bottom, and $L,R$ denoting left and right. Let $L_C$ be the center lamp. In the original figure, face 2 uses top-left and bottom-right, while face 3 uses top-right and bottom-left plus center; the two diagonals must therefore have different controls.^[ref] The required OR gate decoder isFor example, only the center is high in state $Q_1$, the first diagonal is high in state $Q_2$, and in state $Q_6$ both outer columns are high while the center is low. This verifies all six layouts directly.

To implement the switch behavior, use a rapid common clock signal and a sampled enable $S$, high while the switch is pressed. Each next-state input is then selected between its advancing value and its own stored value:One multiplexer per D flip-flop implements that selection. While enabled the electronic dice advances; otherwise every D flip-flop reloads its own value and the display holds. The enable supplied to this synchronous design must be stable at sampling edges. A reset or preset facility must establish the specified one-hot initial state: an all-zero ring does not start itself.

With a rapid clock signal, uncertainty in human release timing makes the final face practically unpredictable. The sequential circuit itself is deterministic; this observation alone is not a proof that its six outcomes have equal probabilities.

A serial-in parallel-out shift register is a chain of digital registers driven by the same clock signal. At each active clock edge, the first stage captures the input and every later stage captures the preceding stage's old value. Its parallel outputs expose the successive delayed samples simultaneously.

Let $a_n$ be the current sample and, immediately before its sampling edge, let $h_1=a_{n-1},\dots ,h_{k-1}=a_{n-k+1}$. Feed these signals to combinational logic implementing $f$. ThenOnly $k-1$ stored history stages are needed if the current input is used directly. Alternatively, a $k$-stage shift register exposes all $k$ samples after the edge. A separate output digital register can capture the first arrangement at the edge, giving a fully sampled output. Initialize the history, or regard the first $k-1$ cycles as a filling interval.

Use three positive-edge-triggered D flip-flops, all driven by the same clock signal $CLK$. Write the current binary representation as $B2B1B0$, with $B0$ the least significant bit. The next state is the current value plus one when $A=1$ and minus one when $A=0$, in each case modulo eight. A bit toggles under exclusive or with a one.

For upward counting, $B1$ toggles when $B0=1$, while $B2$ toggles when $B1=B0=1$, the respective carry conditions. For downward counting the corresponding borrow conditions are $B0=0$ and $B1=B0=0$. Define the shared inverted direction $N=\neg A$ and the two direction-match signalsEach $T_i$ is one exactly when $Bi=A$: it equals $Bi$ for upward counting and $\neg Bi$ for downward counting. Thus the Boolean functions for the three D inputs areImplement this with two NOT gates for $N,D_0$, four two-input exclusive or gates for $T_0,T_1,D_1,D_2$, and one two-input AND gate. Connect $D_i$ to the D flip-flop whose output is $Bi$; feed the three outputs back into the indicated gates. All three flip-flops capture simultaneously, so each equation uses the old state.

For completeness, the state transition table is

Every three-bit state is valid. A reset may initialize the binary counter to zero if required; counting itself needs no extra state. The direction input must meet the setup time and hold time requirements at the active clock edge.

Use a synchronous binary counter with three positive-edge-triggered D flip-flops, all driven by the same clock signal. Write their outputs $q_2{q}_1{q}_0$, with $q_0$ the least significant bit. The next-state Boolean functions areImplement these with one NOT gate, two exclusive or gates, and one AND gate. Connect each $D_i$ to its corresponding D flip-flop; its output $q_i$ is address line $i$. A reset input clears all three flip-flops to zero, so the first selected sensor is sensor zero.

The state sequence isThe low bit toggles at every clock edge, the middle bit toggles exactly when the old low bit is one, and the high bit toggles exactly when both old lower bits are one. These are precisely the carry conditions for incrementing a three-bit binary representation. Every possible state belongs to the cycle, so there is no unused state requiring recovery. Choose a clock period allowing the combinational logic to settle before the next capture.

The interval between successive designated clock edges of a processor's clock signal. In a synchronous sequential circuit it must be long enough for the required register-to-register propagation and setup timing.