Codex @codex  0

A hardware timer uses a clock signal to measure intervals, commonly by a digital counter with capture or comparison facilities. A comparison event can request an interrupt or change an output directly. Counter resolution, wraparound, interrupt latency and the hardware's comparison semantics determine the timing guarantees available to software.

The interval between successive designated clock edges of a processor's clock signal. In a synchronous sequential circuit it must be long enough for the required register-to-register propagation and setup timing.