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Locate an isolated nanowire first, then align source, drain, dielectric and top-gate patterns to it. A suitable research-device sequence is the following; the semiconductor is unspecified, so contact-barrier and surface-cleaning details cannot be assumed universally ohmic.

Prepare a clean electrically insulating substrate, with alignment marks. Disperse a sparse population of nanowires from the suspension, remove the carrier solvent compatibly, and locate a suitable isolated wire by microscopy. Record its position relative to the marks.

Use aligned electron beam lithography and a suitable lift-off process to open contact regions near the two ends while leaving a central channel. Clean the exposed contact regions without destroying the wire, evaporate gold and lift off. The contacts overlap the ends but do not bridge the central channel; test their electrical behavior before assuming an ohmic response.

In a second aligned pattern, define a central dielectric patch that extends beyond the proposed gate edges. Evaporate the specified silicon monoxide and lift off using a profile that permits film separation. Verify coverage over the wire and absence of pinholes: directional deposition onto curved nanoscale geometry is not automatically conformal.

Define and evaporate a gold top gate over that insulated central patch, with its lead kept electrically separated from the source, drain and wire. Lift off and test gate leakage before extracting transistor characteristics. The dielectric must remain continuous under the gate and overlap its edges; the illustrated central gate is not a third direct metal contact to the semiconductor. Gold and silicon monoxide are used as stipulated, without silently replacing SiO by a different oxide.

Projection lithography images a mask through reduction optics; its resolution scales approximately as $k_1\lambda /\mathrm{NA}$. It offers parallel exposure, high throughput and accurate repeat patterning, but small features demand short wavelengths, large numerical aperture, costly optics and high-quality masks, with a shrinking depth of focus.

Electron beam lithography directly writes a programmable pattern using a focused electron beam. Its much shorter wavelength and small probe permit nanometre-scale features without an optical mask, making it attractive for research prototypes, low-volume devices and mask fabrication. Its limitations are serial writing time, charging of insulating substrates, beam drift, field stitching and forward/backscattering proximity effects in electron-beam lithography. Electron wavelength alone does not set the resist resolution. E-beam is often preferable for a few very small custom structures; projection remains preferable for high-volume repeated manufacture.

A modulation-doped GaAs-AlGaAs electron gas is confined on the GaAs side of the interface. The larger-gap AlGaAs supplies a conduction-band barrier; charge transfer from remote donors and the resulting electric field bend the bands into an approximately triangular well. transverse electronic mode wavefunctions are confined normal to the interface but free in its plane. electrons settle into the well until their electrochemical potential agrees with the donor/contact environment. An undoped spacer separates mobile electrons from ionized donors, reducing impurity scattering. Equilibrium has one Fermi level across the structure; the conduction-band edge is not flat. Surface depletion and the cap also affect the profile. The original drawing illustrates one occupied confinement transverse electronic mode; a single spatial electron gas need not in general imply only one occupied vertical transverse electronic mode.

molecular beam epitaxy can grow a clean GaAs buffer/channel, an undoped AlGaAs spacer, a Si-doped AlGaAs supply region and a protective GaAs cap on a suitable substrate. Control composition, interface quality and background impurities during growth; placing dopants directly in the channel defeats the principal mobility advantage. Define a mesa or isolation region, fabricate low-resistance ohmic contacts to the buried gas, and pattern fine metal split gates by electron beam lithography and the lift-off process. Negative gate bias depletes the underlying gas, leaving a narrow channel between the gates. Check contact resistance, leakage, carrier density and mobility; operation with ballistic electron transport requires channel length shorter than the relevant scattering lengths and smooth confinement on the wavelength scale. The lithographic gap does not equal the electrical width because of lateral depletion.

For a long uniform channel supporting ballistic electron transport, transverse confinement creates thresholds $E_n$ with continuous longitudinal propagation above each threshold. One directed spin branch of a transverse electronic mode has states per length $dk/(2\pi )$ and group velocity $v={\hslash }^{-1}dE/dk$. Hence $vdk/(2\pi )=dE/h$: velocity cancels the one-dimensional density of states. Including two unresolved spin states,For low temperature and small bias, a fully open transverse electronic mode has $T_n(E_F)=1$, givingThe assumptions are ideal reservoirs/contacts, negligible reflection and interactions that would invalidate the independent-subband description, and unresolved spin splitting. A resolved spin branch contributes $e^2/h$. The finite two-terminal electrical resistance is a contact/mode-injection effect, despite the absence of dissipative scattering inside the ideal channel.

For voltage partition in a ballistic constriction, a short saddle has strong local electric-field and electrostatic screening variation near its entrances and barrier, rather than the uniform Ohmic voltage gradient of a diffusive wire. Right-moving incident states inherit the source distribution and left-moving states the drain distribution; there is no unique local equilibrium chemical potential inside an ideal ballistic saddle. The electrostatic potential must be determined self-consistently. In a symmetric rigid-barrier approximation, the barrier follows the mean lead potential and half the electrochemical bias lies on each side. This is a stated approximation, not a universal spatial voltage profile.

For a saddle $U=U_0-m^{\ast }{\omega }_x^2{x}^2/2+m^{\ast }{\omega }_y^2{y}^2/2$, transverse electronic mode thresholds are $E_n=U_0+\hslash {\omega }_y(n+1/2)$. The smooth-barrier transmission is $T_n(E)=[1+\exp (-2\pi (E-E_n)/(\hslash {\omega }_x)){]}^{-1}$, approaching a step for a sharp threshold on the bias/thermal scale.^[ref]

Let ${\mu }_{S,D}=E_F\pm eV/2$ and assume no additional bias dependence of $T_n$. At zero temperature,When the source and drain sample $N+1$ and $N$ thresholds, the differential electrical conductance is $(N+1/2)2e^2/h$. These half plateaus arise from the two ends of the bias window, not fractional carriers. The dc ratio $I/V$ need not share their plateau values. Heating, spin splitting and interaction-induced features must be distinguished experimentally.

In bias spectroscopy of one-dimensional subbands, plot differential electrical conductance or its gate derivative against gate bias and source-drain bias. Threshold branches occur where $E_n(V_g)={\mu }_S$ or ${\mu }_D$. When one bias-window edge meets $E_n$ and the other $E_{n+1}$,Thus the intersections of adjacent threshold branches calibrate the one-dimensional spacing directly in energy. A gate lever arm $\alpha =-e^{-1}\partial E_n/\partial V_g$ can then convert gate intervals to energy; it should be measured rather than guessed. Asymmetric bias partition, a moving barrier or a gate-dependent spacing modifies slopes and plateau weights, requiring the corresponding self-consistent bias model.