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Incoming links: Finite-state machine
Automaton state Created 2026-10-14 Updated 2026-10-25
An automaton state is one possible memory configuration of a finite-state machine. The initial automaton state is the starting configuration; accepting automaton states indicate successful recognition when the whole word has been read.
Bit-serial comparator 2026-10-31
A digital comparator processes one pair of bits per clock cycle, storing a comparison result in a finite-state machine. For least-significant-first unsigned input, a new unequal pair overrides the stored result, while equal bits preserve it: the newest unequal pair has the greatest place value seen so far.
Buffer cache state model 2026-10-14
Use one fixed-size buffered device block per buffer cache key, serialized operations, successful reads and writes, and no outside changes to the backing contents. Record an absent state or a reserved key with validity , dirty flag , and retained-reference count . The bits describe contents, while the nonnegative integer describes lifetime. Every dirty buffer is valid, so implies . Reservation begins at ; successful fill changes only to 1. Modifying a valid retained structure sets . Releasing a caller changes , not or .
Buffer cache validity, dirty buffers and retained references impose different state-transition rules
. Details. The first diagram separates contents transitions from reference transitions. Buffer cache writeback temporarily retains the structure while transferring its contents; that internal reference is acquired and released inside the single serialized operation shown. Buffer cache eviction requires a valid clean buffer with . The diagram omits read errors, explicit cancellation of invalid reservations, concurrent writes, invalidation and journal ordering. In particular, a journal can forbid otherwise possible buffer cache writeback until its write-ahead logging dependencies are satisfied.
For a small independent check, bound to . Starting absent, allow reservation, acquisition, successful fill, modification, successful buffer cache writeback, release of a valid retained structure, and eligible buffer cache eviction. Exactly nine abstract states are reachable: absent, two invalid reservations with , and six valid states combining with . Every transition preserves ; the only eviction source has . This bounded finite-state machine check supports these safety rules, not a claim that work always completes.
Don't-care term 2026-10-31
An input combination at which a Boolean function's specification imposes no required output value. Karnaugh map minimization may assign either value independently to simplify the implemented Boolean circuit. The resulting circuit still assigns a definite output to every input. An unused finite-state machine encoding is therefore an optimization opportunity, but its eventual transitions must be checked if recovery from that encoding matters.
Finite-state machine 2026-10-14
A finite-state machine processes inputs using a finite set of automaton states and input-dependent automaton transitions. An automaton state records everything the machine remembers; an automaton transition says how that memory changes on the next symbol. A finite-state machine may also emit outputs. Here the emphasis is on recognizing a formal language: start in a designated automaton state, read a word from an alphabet, and accept exactly when the final automaton state is designated accepting.
Finite memory does not impose a maximum input length. A finite-state machine can read arbitrarily long words, revisiting its automaton states indefinitely. The restriction is that the part already read must be compressed into one of finitely many summaries. For divisibility by three, a word of binary digits can describe an enormous integer, yet its congruence class modulo three is all that the machine needs to retain. Two already-read words giving the same automaton state behave identically under every subsequent continuation in a DFA.
This makes finite-state machines useful whenever past details can be forgotten safely: checking whether a sequence of commands follows an allowed order, or recognizing a pattern with a regular expression. The beautiful design question is which distinctions about the past matter to the future. DFA minimization makes that question precise by merging indistinguishable states of a deterministic finite automaton. Both DFAs and NFAs recognize exactly the regular languages.
Finite-state strategy 2026-10-25
A history-dependent pure strategy represented by a finite-state machine with an initial automaton state, an action output for each state, and an automaton transition after each observed completed joint action. A grim trigger strategy uses a following state and an absorbing punishment state. Two such deterministic machines jointly form a finite deterministic state system, so their action path is eventually periodic. Its long-run average payoffs are the averages over the eventual cycle; a finite initial prefix has vanishing weight.
Interrupt-driven pulse sequencer Created 2026-10-25 Updated 2026-10-31
A pulse sequencer can separate event capture from output timing. A short interrupt handler acknowledges the event latch and increments a pending count. An independent finite-state machine consumes one count on entering
ON, changes to GAP after the pulse width, and enters IDLE only after the mandatory off interval. Even an empty queue must not bypass GAP: an arrival immediately after light-off would otherwise start too soon.The pending count equals recorded events minus started pulses. A critical section protects its read-modify-write operations; declaring shared state as in volatile-qualified objects in C does not alone make each update an atomic operation. Separate sequencers for different channels allow simultaneous pulses while one hardware timer schedules their earliest deadline. Finite queue capacity, detector rearming and dispatch resolution remain explicit assumptions.
Moore machine 2026-10-25
A Moore machine is a finite-state machine whose output depends only on the current state. In a clocked implementation, a state entered at a clock edge determines the following period's output. Specifying an initial state is necessary to define startup behavior.
Nondeterministic finite automaton Created 2026-09-24 Updated 2026-10-14
A nondeterministic finite automaton allows a set of possible destinations for each automaton state and input symbol. Without the extra moves permitted in an Epsilon-NFA, replace the DFA function by , where is the power set. A word is accepted when at least one path consumes all its symbols and ends in an accepting automaton state. These choices express existential quantification, not probability: no chance of choosing a particular path is assigned. One successful path suffices even if other paths fail.
Consider a three-state NFA accepting exactly the words of binary digits ending in . Its initial automaton state loops on both and ; it also has an automaton transition , followed by . Only is accepting, and all unlisted automaton transitions are absent. Staying at skips an arbitrary beginning; leaving it guesses that the current zero starts the final two symbols.
The word accepts along . The word accepts along . The word rejects: a path reaching after cannot consume the remaining zero, while the other paths end outside . Thus finding somewhere is insufficient; it must occur at the end.
To simulate the NFA deterministically, retain the set of all currently possible automaton states. The powerset construction updates by taking the union of the destinations of its members. Here only , , and are reachable, although the full power set has eight members. Reading gives , which rejects. In general, an -state NFA yields a DFA with at most automaton states. Nondeterminism can simplify a description, while the powerset construction keeps the memory finite.
The second generator checks all 511 words of up to eight binary digits against the direct test of whether their final two symbols are . Exactly 127 accept, and only the three listed sets of automaton states occur. In particular, the empty word rejects for this NFA.
Michael O. Rabin and Dana Scott's 1959 paper studied finite-state machines as recognizers with finite internal memory. Its section 5 defines NFAs through successful paths, and theorem 11 proves their equivalence to DFAs by the powerset construction. This gives a historical source for the distinction between many possible paths and greater recognition power: [ref]
https://www.cs.cmu.edu/~lblum/flac/Handouts_pdf/rs.pdf. Rabin and Scott, Finite Automata and Their Decision Problems, pp. 120–121
.Against Tit for tat, let be an arbitrary deviator's action at round , and set to encode the opponent's initial cooperation. The opponent then plays . Define and . The four possible transitions giveThus every stage payoff is at most . The telescoping sum yields the uniform payoff bound against Tit for tat:After division by , no long-run average payoff can exceed three. The bound applies to every action sequence, so in particular it covers every finite-state machine representing a unilateral deviation. Mutual Tit for tat produces in every round and gives each player three. Neither player can improve, proving is a Nash equilibrium.
Another pair is . Here grim trigger initially cooperates and continues cooperating until the opponent first defects, after which it defects forever. Both strategies are two-state finite-state machines: Tit for tat records the opponent's previous action, while grim trigger records whether defection has ever occurred. Their prescribed play again consists entirely of cooperation and gives .
The player using grim trigger faces Tit for tat, so every unilateral deviation is bounded by the same telescoping sum and cannot improve on three. The player using Tit for tat faces grim trigger. If that player never defects, the payoff remains three. If the first defection occurs at a finite round , it gives a one-time payoff six; thereafter the opponent always defects, against which each subsequent payoff is at most one. Any finite initial prefix has zero contribution to the long-run average payoff, so such a unilateral deviation has limiting upper average at most one. It cannot improve on three either. Both players are therefore best responses, proving the second claimed Nash equilibrium.
For deterministic finite-state machines, the joint state path is eventually periodic, so the displayed averages have a limit. The first bound also controls the limiting upper average for arbitrary action sequences, making the no-improvement argument stronger than an enumeration of finite-state deviations. Notice that equality in the bound permits alternating exploitation to average three: equilibrium requires absence of a strict improvement, not uniqueness of a best response.
Use a three-state Moore machine for a rearmable one-cycle pulse generator. Call the states
Ready, Pulse, and Wait. Their outputs are respectively , and initialize in Ready. Labels below are the sampled input pair ab; because simultaneous ones are unspecified, choose reset priority for 11.
Rearmable one-cycle pulse generator and reproduction of the specified timing behavior
. Details. 
The complete chosen state transition table is
| State | |||||
|---|---|---|---|---|---|
Ready | Ready | Ready | Pulse | Ready | |
Pulse | Wait | Ready | Wait | Ready | |
Wait | Wait | Ready | Wait | Ready |
A sampled trigger
10 causes a pulse only in Ready. Leaving Pulse unconditionally on the next edge keeps its output high for exactly one clock period, even if a remains high. In Wait, further triggers are ignored until a sampled reset rearms the finite-state machine.The crucial transition is
Pulse --01--> Ready. If reset occurs in the cycle immediately following a trigger, this transition both ends the current pulse and rearms the circuit. The next trigger then produces a pulse after just one intervening low-output cycle. Sending every exit from Pulse to Wait would lose that reset and fail the alternate-cycle requirement. This behavior is explicitly visible in the last three pulses of the original timing diagram.[ref]Functional programming, data structures and algorithms, procedural programming, and digital hardware examination paper by the University of Oxford (2003). Printed p. 8, Question 10(b)(iii), last reset and trigger alternations
For the sixteen sampled pairs in that diagram, numbering the first edge as 1,
z is high just after edges and low after every other edge. Equivalently,The two low-output states cannot be merged: the same future trigger must produce a pulse from Ready and be ignored from Wait. A separate high-output state is needed to hold the one-cycle pulse, explaining the three-state design.The finite-state machine retains its state on input
00 or 11, moves to Lt on 01, and moves to Gt on 10. Here each input label is the pair ab, not a pair of outputs. The following state-transition diagram shows every valid-state transition; a diagonal input is stronger than all previous comparison history because it arrives at a more significant position.
Least-significant-first comparator transitions and Karnaugh maps
. Details. 
Equivalently the complete transition rule isThe state-transition diagram starts at
Eq, representing the comparison of two empty, hence zero-valued, bit strings.A short interrupt handler should acknowledge the detector and count work; a timed finite-state machine should generate the flashes. A Boolean “someone arrived” variable cannot preserve several queued detections. This is an interrupt-driven pulse sequencer. Initialise the light off, the pending-event counter to zero and the sequencer to
IDLE before enabling interrupts.In the following pseudocode, interrupt acknowledgement uses the source-specified operation of writing zero. The atomic operation and timer calls name abstract services, not undocumented device registers of a particular microcontroller.
eye_handler():
if EYE_DETECTED != 0:
EYE_DETECTED = 0
pending = pending + 1
try_take_event():
briefly mask the detector interrupt
if pending == 0: taken = false
else: pending = pending - 1; taken = true
restore the previous interrupt mask
return taken
service(now):
if state == ON and elapsed(now, started) >= one_second:
LIGHT = 0
state = GAP
started = now
if state == GAP and elapsed(now, started) >= one_second:
state = IDLE
if state == IDLE and try_take_event():
LIGHT = 1
state = ON
started = nowThe main program repeatedly handles a new event or the next timer deadline and calls
service. The ON state lasts one second; every completed flash enters GAP, even if the queue is empty at that instant. An arrival during that gap must wait for it to expire. Otherwise turning the light off and immediately treating the device as idle could allow a new flash too soon. Once a gap has expired, a queued event starts a new flash; if no work is pending the device remains idle. Removing a pending event only when a flash starts gives one completed flash per consumed event.An interrupt can arrive during the main program's decrement. Without a critical section, its increment can be overwritten by a race condition. Merely declaring the counter
volatile, as in volatile-qualified objects in C, does not make the decrement an atomic operation. Short interrupt masking, or an appropriate atomic operation, protects it; interrupts must remain enabled during the one-second intervals so that detections continue to be recorded.A calibrated busy-wait loop is simple, but occupies the CPU and its duration depends on instruction timing, compiler transformations and time spent in interrupts. Polling a hardware timer avoids calibration dependence but still consumes CPU while polling. A timer interrupt or timer comparison deadline permits useful work or safe sleeping between transitions and is preferable for precise timing. If sleeping, the test for queued work and entry into sleep must avoid a lost wake-up. By the modulo-counter elapsed-time identity, a wrapping digital counter is usable if elapsed-time subtraction is unsigned and the real observation interval is less than its modulus; a wide enough counter or suitable bounded intervals make this explicit. Software dispatch adds bounded latency, so the specification is achieved to timer/interrupt-service resolution; stricter physical pulse-width requirements call for hardware output comparison or a suitably prioritised timer handler.
Finally, the device register is only a single-bit event latch. Two physical detections before acknowledgement may coalesce, so no software can recover their multiplicity from that bit alone. The event counter must also have enough capacity for the allowed backlog; indefinitely many arrivals faster than one flash every two seconds cannot be guaranteed with finite storage. These are explicit hardware/rate assumptions, not missing input files. Keeping the handler short minimises the rearming interval but cannot abolish those limitations.
Maintain a counter and independent timed finite-state machine for each detector–light pair, while sharing the interrupt scan and timer infrastructure. Blocking for one channel's flash would unnecessarily delay every other channel.
eye_handler():
for i in all_channels:
if EYE_DETECTED[i] != 0:
EYE_DETECTED[i] = 0
pending[i] = pending[i] + 1
main_event_loop():
initialise each LIGHT[i] = 0
initialise pending[i] = 0, state[i] = IDLE
enable detector interrupts
forever:
now = monotonic_timer_snapshot()
for i in all_channels:
service_channel(i, now)
arrange the next wake-up for new work or the earliest deadlineservice_channel is the three-state sequencer from (a), with its own started[i] and an interrupt-safe try_take_event(i). Shared interrupt demultiplexing uses separate if tests, not an else if chain: simultaneous pending detectors must all be acknowledged and counted. If a new detector becomes pending during the scan, the controller must retrigger while a flag remains set or the handler must rescan appropriately; the exact interrupt controller semantics must be checked rather than assuming a single scan can never miss an edge.One hardware timer can schedule the earliest active channel deadline. On its expiry, service every due channel and rearm for the next deadline; a periodic tick with adequate resolution is a simpler alternative. Detectors and the timer can then interleave without serial one-second waits. The handler/main-program counter accesses need the same short critical section protection as in (a). Keep timing state in one execution context, or protect it too if both a timer handler and the main program modify it.
The loop invariants are per channel: the pending count equals recorded but unstarted events,
ON means that channel's light is on, and GAP prevents a new flash until one second after its preceding light-off transition. Different channels may flash simultaneously. The event latch rearming limitation, finite backlog capacity and timer-resolution qualifications apply independently to each channel. These cannot be solved by replacing several event counters with one global Boolean variable.Let be the input sampled at clock edge . The desired registered output after that edge is . Only the last two high samples matter: a longer high run still has two high samples immediately before its first low sample.
A direct synchronous 110 detector uses three D flip-flops, holding , with a common clock and initial state zero. Use the following next-state equations, all evaluated from the old state and the input at the active clock edge:After an edge, records the latest sample and records whether the latest two samples were high. The final equation consequently produces the required pulse from the preceding two-high state and the new low sample. A synchronous reset sets all three state bits to zero. The output is the stored
z flip-flop value, so it changes only after clock edges; exposing the unregistered expression would let input transitions between edges alter the output.
Original sampled-input and registered-output trace for a synchronous 110 detector
. Details. 
An equivalent finite-state machine has states
R (no current high run), H (one high), HH (at least two highs), and P (the pulse state). Its output is one only in P:The pulse cannot last two cycles: after the low input that creates it, is zero, so the next output is zero regardless of the next input. The detector rearms without a global stop and handles repeated patterns indefinitely. The three-flip-flop construction is deliberately direct; minimum storage was not required.
Four state bits are necessary and sufficient. For each output value, distinguish three armed situations, remembering a trailing high run of length , and three disarmed situations, remembering a trailing low run of length . Thus a direct minimal behavioural description hasAll twelve situations are reachable. Different output values are immediately distinguishable. Within an armed group, a suitable number of high samples distinguishes the three run lengths by when the next toggle occurs. Within a disarmed group, a suitable number of low samples followed by three highs distinguishes the three rearming distances. An armed situation and a disarmed situation of the same output value are distinguished by an all-high continuation: the armed one eventually toggles and the disarmed one does not. Hence these twelve situations cannot be merged in a finite-state machine implementing the specification.
The shared-history design in (c) uses four bits, meeting this lower bound. Its sixteen encoded states have some behaviourally equivalent histories, so its encoding need not use only twelve combinations. Building two separate copies of (a) plus the two-bit module (b) would use six state-bearing elements; sharing the input history saves two.
Read-only memory 2026-10-31
A memory read through an address whose contents are fixed during ordinary operation. Used as a Boolean function lookup table, address bits select one of words, each holding output bits, so the logical table capacity is bits. A finite-state machine can store its next-state function in such a table while separate flip-flops store the current state.
Self-starting finite-state machine 2026-10-31
A hardware finite-state machine whose implemented transitions eventually leave every unused state encoding and enter the intended valid state set. If recovery must hold for arbitrary inputs, it is not enough that some input sequence can escape: there must be no indefinitely surviving unused-state path under any input sequence. Since the unused-state graph is finite, absence of a directed cycle among unused states gives a uniform finite recovery bound. A reset or initialization rule may still be required to give the valid state its intended meaning.
State encoding 2026-10-31
An injective assignment of abstract finite-state machine states to stored bit patterns. distinct states require at least binary storage elements. Encodings with unused patterns can simplify Boolean functions through don't-care conditions, but the implemented next-state equations determine what those unused patterns actually do.
State machine 2026-10-31
A computational model with an internal state and transition rule, together with an initial state and optional observation and stopping functions. The state space need not be finite; a finite-state machine is the special case with finitely many states. A trace records observations along transitions. An interface providing only reset, update, stopping and observation operations does not by itself provide copying or rollback; a trace iterator can revisit saved observations without reversing machine effects.